Corners

Todo

document

Lower left

Todo

document

LL.V2

This tile is used on Virtex 2.

LL.V2 bittile 0
RowColumn
0123
0 ----
1 ----
2 ----
3 ----
4 ----
5 ----
6 ----
7 ----
8 ----
9 ----
10 ----
11 ----
12 ----
13 ----
14 ----
15 ----
16 ----
17 ----
18 ----
19 ----
20 ----
21 ----
22 ----
23 ----
24 ----
25 ----
26 ----
27 ----
28 ----
29 ----
30 ----
31 --DCI0:TEST_ENABLEDCI0:FORCE_DONE_HIGH
32 --DCI0:PMASK_TERM_SPLIT[4]DCI0:PMASK_TERM_SPLIT[3]
33 --DCI0:PMASK_TERM_SPLIT[2]DCI0:PMASK_TERM_SPLIT[1]
34 --DCI0:PMASK_TERM_SPLIT[0]DCI0:PMASK_TERM_VCC[4]
35 --DCI0:PMASK_TERM_VCC[3]DCI0:PMASK_TERM_VCC[2]
36 --DCI0:PMASK_TERM_VCC[1]DCI0:PMASK_TERM_VCC[0]
37 --DCI0:NMASK_TERM_SPLIT[4]DCI0:NMASK_TERM_SPLIT[3]
38 --DCI0:NMASK_TERM_SPLIT[2]DCI0:NMASK_TERM_SPLIT[1]
39 --DCI0:NMASK_TERM_SPLIT[0]-
40 ----
41 ----
42 --DCI0:ENABLE-
43 ----
44 ---DCI0:LVDSBIAS[8]
45 --DCI0:LVDSBIAS[7]DCI0:LVDSBIAS[6]
46 --DCI0:LVDSBIAS[5]DCI0:LVDSBIAS[4]
47 --DCI0:LVDSBIAS[3]DCI0:LVDSBIAS[2]
48 --DCI0:LVDSBIAS[1]DCI0:LVDSBIAS[0]
LL.V2 bittile 1
RowColumn
012345678910111213141516171819
0 --------------------
1 --------------------
2 --------------------
3 --------------------
4 --------------------
5 --------------------
6 --------DCI1:PMASK_TERM_VCC[1]DCI1:TEST_ENABLE-DCI1:NMASK_TERM_SPLIT[4]DCI1:LVDSBIAS[1]---MISC:DISABLEBANDGAPMISC:BCLK_DIV2[2]-MISC:RAISEVGG[0]
7 --------DCI1:PMASK_TERM_VCC[2]DCI1:PMASK_TERM_SPLIT[3]DCI1:ENABLEDCI1:NMASK_TERM_SPLIT[1]DCI1:LVDSBIAS[2]DCI1:LVDSBIAS[8]--MISC:M2PIN[0]MISC:BCLK_DIV2[3]-MISC:ZCLK_DIV2[3]
8 --------DCI1:PMASK_TERM_VCC[0]DCI1:FORCE_DONE_HIGH-DCI1:NMASK_TERM_SPLIT[3]DCI1:LVDSBIAS[0]---MISC:M2PIN[1]MISC:BCLK_DIV2[4]-MISC:RAISEVGG[1]
9 --------DCI1:PMASK_TERM_SPLIT[0]DCI1:PMASK_TERM_SPLIT[1]--DCI1:LVDSBIAS[5]DCI1:LVDSBIAS[6]--MISC:M1PIN[0]MISC:BCLK_DIV2[1]MISC:DCI_ALTVRMISC:ZCLK_DIV2[1]
10 --------DCI1:PMASK_TERM_VCC[4]DCI1:PMASK_TERM_SPLIT[4]-DCI1:NMASK_TERM_SPLIT[2]DCI1:LVDSBIAS[3]---MISC:M0PIN[0]MISC:BCLK_DIV2[0]MISC:DCI_CLK_ENABLEMISC:ZCLK_DIV2[4]
11 --------DCI1:PMASK_TERM_VCC[3]DCI1:PMASK_TERM_SPLIT[2]-DCI1:NMASK_TERM_SPLIT[0]DCI1:LVDSBIAS[4]DCI1:LVDSBIAS[7]--MISC:M0PIN[1]MISC:M1PIN[1]MISC:ZCLK_DIV2[0]MISC:ZCLK_DIV2[2]
DCI0:ENABLE[0, 2, 42]
DCI0:FORCE_DONE_HIGH[0, 3, 31]
DCI0:TEST_ENABLE[0, 2, 31]
DCI1:ENABLE[1, 10, 7]
DCI1:FORCE_DONE_HIGH[1, 9, 8]
DCI1:TEST_ENABLE[1, 9, 6]
MISC:DCI_ALTVR[1, 18, 9]
MISC:DCI_CLK_ENABLE[1, 18, 10]
MISC:DISABLEBANDGAP[1, 16, 6]
Non-inverted[0]
DCI0:NMASK_TERM_SPLIT[0, 2, 37][0, 3, 37][0, 2, 38][0, 3, 38][0, 2, 39]
DCI0:PMASK_TERM_SPLIT[0, 2, 32][0, 3, 32][0, 2, 33][0, 3, 33][0, 2, 34]
DCI0:PMASK_TERM_VCC[0, 3, 34][0, 2, 35][0, 3, 35][0, 2, 36][0, 3, 36]
DCI1:NMASK_TERM_SPLIT[1, 11, 6][1, 11, 8][1, 11, 10][1, 11, 7][1, 11, 11]
DCI1:PMASK_TERM_SPLIT[1, 9, 10][1, 9, 7][1, 9, 11][1, 9, 9][1, 8, 9]
DCI1:PMASK_TERM_VCC[1, 8, 10][1, 8, 11][1, 8, 7][1, 8, 6][1, 8, 8]
MISC:BCLK_DIV2[1, 17, 8][1, 17, 7][1, 17, 6][1, 17, 9][1, 17, 10]
MISC:ZCLK_DIV2[1, 19, 10][1, 19, 7][1, 19, 11][1, 19, 9][1, 18, 11]
Non-inverted[4][3][2][1][0]
DCI0:LVDSBIAS[0, 3, 44][0, 2, 45][0, 3, 45][0, 2, 46][0, 3, 46][0, 2, 47][0, 3, 47][0, 2, 48][0, 3, 48]
DCI1:LVDSBIAS[1, 13, 7][1, 13, 11][1, 13, 9][1, 12, 9][1, 12, 11][1, 12, 10][1, 12, 7][1, 12, 6][1, 12, 8]
Non-inverted[8][7][6][5][4][3][2][1][0]
MISC:M0PIN[1, 16, 11][1, 16, 10]
MISC:M1PIN[1, 17, 11][1, 16, 9]
MISC:M2PIN[1, 16, 8][1, 16, 7]
PULLUP00
PULLDOWN01
PULLNONE10
MISC:RAISEVGG[1, 19, 8][1, 19, 6]
Non-inverted[1][0]

LL.V2P

This tile is used on Virtex 2 Pro.

LL.V2P bittile 0
RowColumn
0123
0 ----
1 ----
2 ----
3 ----
4 ----
5 ----
6 ----
7 ----
8 ----
9 ----
10 ----
11 ----
12 ----
13 ----
14 ----
15 ----
16 ----
17 ----
18 ----
19 ----
20 ----
21 ----
22 ----
23 ----
24 ----
25 ----
26 ----
27 ----
28 ----
29 ----
30 ----
31 --DCI0:TEST_ENABLEDCI0:FORCE_DONE_HIGH
32 --DCI0:PMASK_TERM_SPLIT[4]DCI0:PMASK_TERM_SPLIT[3]
33 --DCI0:PMASK_TERM_SPLIT[2]DCI0:PMASK_TERM_SPLIT[1]
34 --DCI0:PMASK_TERM_SPLIT[0]DCI0:PMASK_TERM_VCC[4]
35 --DCI0:PMASK_TERM_VCC[3]DCI0:PMASK_TERM_VCC[2]
36 --DCI0:PMASK_TERM_VCC[1]DCI0:PMASK_TERM_VCC[0]
37 --DCI0:NMASK_TERM_SPLIT[4]DCI0:NMASK_TERM_SPLIT[3]
38 --DCI0:NMASK_TERM_SPLIT[2]DCI0:NMASK_TERM_SPLIT[1]
39 --DCI0:NMASK_TERM_SPLIT[0]DCI0:QUIET
40 ----
41 ----
42 --DCI0:ENABLE-
43 ----
44 ---DCI0:LVDSBIAS[8]
45 --DCI0:LVDSBIAS[7]DCI0:LVDSBIAS[6]
46 --DCI0:LVDSBIAS[5]DCI0:LVDSBIAS[4]
47 --DCI0:LVDSBIAS[3]DCI0:LVDSBIAS[2]
48 --DCI0:LVDSBIAS[1]DCI0:LVDSBIAS[0]
LL.V2P bittile 1
RowColumn
012345678910111213141516171819
0 --------------------
1 --------------------
2 --------------------
3 --------------------
4 --------------------
5 --------------------
6 --------DCI1:PMASK_TERM_VCC[1]DCI1:TEST_ENABLE-DCI1:NMASK_TERM_SPLIT[4]DCI1:LVDSBIAS[1]---MISC:DISABLEBANDGAPMISC:BCLK_DIV2[2]-MISC:RAISEVGG[0]
7 --------DCI1:PMASK_TERM_VCC[2]DCI1:PMASK_TERM_SPLIT[3]DCI1:ENABLEDCI1:NMASK_TERM_SPLIT[1]DCI1:LVDSBIAS[2]DCI1:LVDSBIAS[8]--MISC:M2PIN[0]MISC:BCLK_DIV2[3]-MISC:ZCLK_DIV2[3]
8 --------DCI1:PMASK_TERM_VCC[0]DCI1:FORCE_DONE_HIGH-DCI1:NMASK_TERM_SPLIT[3]DCI1:LVDSBIAS[0]---MISC:M2PIN[1]MISC:BCLK_DIV2[4]MISC:DISABLEVGGGENERATIONMISC:RAISEVGG[1]
9 --------DCI1:PMASK_TERM_SPLIT[0]DCI1:PMASK_TERM_SPLIT[1]-DCI1:QUIETDCI1:LVDSBIAS[5]DCI1:LVDSBIAS[6]--MISC:M1PIN[0]MISC:BCLK_DIV2[1]-MISC:ZCLK_DIV2[1]
10 --------DCI1:PMASK_TERM_VCC[4]DCI1:PMASK_TERM_SPLIT[4]-DCI1:NMASK_TERM_SPLIT[2]DCI1:LVDSBIAS[3]---MISC:M0PIN[0]MISC:BCLK_DIV2[0]MISC:DCI_CLK_ENABLEMISC:ZCLK_DIV2[4]
11 --------DCI1:PMASK_TERM_VCC[3]DCI1:PMASK_TERM_SPLIT[2]-DCI1:NMASK_TERM_SPLIT[0]DCI1:LVDSBIAS[4]DCI1:LVDSBIAS[7]--MISC:M0PIN[1]MISC:M1PIN[1]MISC:ZCLK_DIV2[0]MISC:ZCLK_DIV2[2]
DCI0:ENABLE[0, 2, 42]
DCI0:FORCE_DONE_HIGH[0, 3, 31]
DCI0:QUIET[0, 3, 39]
DCI0:TEST_ENABLE[0, 2, 31]
DCI1:ENABLE[1, 10, 7]
DCI1:FORCE_DONE_HIGH[1, 9, 8]
DCI1:QUIET[1, 11, 9]
DCI1:TEST_ENABLE[1, 9, 6]
MISC:DCI_CLK_ENABLE[1, 18, 10]
MISC:DISABLEBANDGAP[1, 16, 6]
MISC:DISABLEVGGGENERATION[1, 18, 8]
Non-inverted[0]
DCI0:NMASK_TERM_SPLIT[0, 2, 37][0, 3, 37][0, 2, 38][0, 3, 38][0, 2, 39]
DCI0:PMASK_TERM_SPLIT[0, 2, 32][0, 3, 32][0, 2, 33][0, 3, 33][0, 2, 34]
DCI0:PMASK_TERM_VCC[0, 3, 34][0, 2, 35][0, 3, 35][0, 2, 36][0, 3, 36]
DCI1:NMASK_TERM_SPLIT[1, 11, 6][1, 11, 8][1, 11, 10][1, 11, 7][1, 11, 11]
DCI1:PMASK_TERM_SPLIT[1, 9, 10][1, 9, 7][1, 9, 11][1, 9, 9][1, 8, 9]
DCI1:PMASK_TERM_VCC[1, 8, 10][1, 8, 11][1, 8, 7][1, 8, 6][1, 8, 8]
MISC:BCLK_DIV2[1, 17, 8][1, 17, 7][1, 17, 6][1, 17, 9][1, 17, 10]
MISC:ZCLK_DIV2[1, 19, 10][1, 19, 7][1, 19, 11][1, 19, 9][1, 18, 11]
Non-inverted[4][3][2][1][0]
DCI0:LVDSBIAS[0, 3, 44][0, 2, 45][0, 3, 45][0, 2, 46][0, 3, 46][0, 2, 47][0, 3, 47][0, 2, 48][0, 3, 48]
DCI1:LVDSBIAS[1, 13, 7][1, 13, 11][1, 13, 9][1, 12, 9][1, 12, 11][1, 12, 10][1, 12, 7][1, 12, 6][1, 12, 8]
Non-inverted[8][7][6][5][4][3][2][1][0]
MISC:M0PIN[1, 16, 11][1, 16, 10]
MISC:M1PIN[1, 17, 11][1, 16, 9]
MISC:M2PIN[1, 16, 8][1, 16, 7]
PULLUP00
PULLDOWN01
PULLNONE10
MISC:RAISEVGG[1, 19, 8][1, 19, 6]
Non-inverted[1][0]

Upper left

Todo

document

UL.V2

This tile is used on Virtex 2.

UL.V2 bittile 0
RowColumn
0123
0 ----
1 ----
2 ----
3 ----
4 ----
5 ----
6 ----
7 ----
8 ----
9 ----
10 ----
11 ----
12 ----
13 ----
14 ----
15 ----
16 ----
17 ----
18 ----
19 ----
20 ----
21 ----
22 ----
23 ----
24 ----
25 ----
26 ----
27 ----
28 ----
29 ----
30 ----
31 --DCI0:TEST_ENABLEDCI0:FORCE_DONE_HIGH
32 --DCI0:PMASK_TERM_SPLIT[4]DCI0:PMASK_TERM_SPLIT[3]
33 --DCI0:PMASK_TERM_SPLIT[2]DCI0:PMASK_TERM_SPLIT[1]
34 --DCI0:PMASK_TERM_SPLIT[0]DCI0:PMASK_TERM_VCC[4]
35 --DCI0:PMASK_TERM_VCC[3]DCI0:PMASK_TERM_VCC[2]
36 --DCI0:PMASK_TERM_VCC[1]DCI0:PMASK_TERM_VCC[0]
37 --DCI0:NMASK_TERM_SPLIT[4]DCI0:NMASK_TERM_SPLIT[3]
38 --DCI0:NMASK_TERM_SPLIT[2]DCI0:NMASK_TERM_SPLIT[1]
39 --DCI0:NMASK_TERM_SPLIT[0]-
40 ----
41 ----
42 --DCI0:ENABLE-
43 ----
44 ---DCI0:LVDSBIAS[8]
45 --DCI0:LVDSBIAS[7]DCI0:LVDSBIAS[6]
46 --DCI0:LVDSBIAS[5]DCI0:LVDSBIAS[4]
47 --DCI0:LVDSBIAS[3]DCI0:LVDSBIAS[2]
48 --DCI0:LVDSBIAS[1]DCI0:LVDSBIAS[0]
UL.V2 bittile 1
RowColumn
012345678910111213
0 --------------
1 --------------
2 --------------
3 --------------
4 --------------
5 --------------
6 ------MISC:TDIPIN[1]-DCI1:PMASK_TERM_VCC[1]DCI1:TEST_ENABLE-DCI1:NMASK_TERM_SPLIT[4]DCI1:LVDSBIAS[1]-
7 ------MISC:TDIPIN[0]-DCI1:PMASK_TERM_VCC[2]DCI1:PMASK_TERM_SPLIT[3]DCI1:ENABLEDCI1:NMASK_TERM_SPLIT[1]DCI1:LVDSBIAS[2]DCI1:LVDSBIAS[8]
8 ------MISC:HSWAPENPIN[1]-DCI1:PMASK_TERM_VCC[0]DCI1:FORCE_DONE_HIGH-DCI1:NMASK_TERM_SPLIT[3]DCI1:LVDSBIAS[0]-
9 ------MISC:TEST_LL-DCI1:PMASK_TERM_SPLIT[0]DCI1:PMASK_TERM_SPLIT[1]--DCI1:LVDSBIAS[5]DCI1:LVDSBIAS[6]
10 ------MISC:HSWAPENPIN[0]-DCI1:PMASK_TERM_VCC[4]DCI1:PMASK_TERM_SPLIT[4]-DCI1:NMASK_TERM_SPLIT[2]DCI1:LVDSBIAS[3]-
11 ------MISC:PROGPIN-DCI1:PMASK_TERM_VCC[3]DCI1:PMASK_TERM_SPLIT[2]-DCI1:NMASK_TERM_SPLIT[0]DCI1:LVDSBIAS[4]DCI1:LVDSBIAS[7]
DCI0:ENABLE[0, 2, 42]
DCI0:FORCE_DONE_HIGH[0, 3, 31]
DCI0:TEST_ENABLE[0, 2, 31]
DCI1:ENABLE[1, 10, 7]
DCI1:FORCE_DONE_HIGH[1, 9, 8]
DCI1:TEST_ENABLE[1, 9, 6]
MISC:TEST_LL[1, 6, 9]
Non-inverted[0]
DCI0:NMASK_TERM_SPLIT[0, 2, 37][0, 3, 37][0, 2, 38][0, 3, 38][0, 2, 39]
DCI0:PMASK_TERM_SPLIT[0, 2, 32][0, 3, 32][0, 2, 33][0, 3, 33][0, 2, 34]
DCI0:PMASK_TERM_VCC[0, 3, 34][0, 2, 35][0, 3, 35][0, 2, 36][0, 3, 36]
DCI1:NMASK_TERM_SPLIT[1, 11, 6][1, 11, 8][1, 11, 10][1, 11, 7][1, 11, 11]
DCI1:PMASK_TERM_SPLIT[1, 9, 10][1, 9, 7][1, 9, 11][1, 9, 9][1, 8, 9]
DCI1:PMASK_TERM_VCC[1, 8, 10][1, 8, 11][1, 8, 7][1, 8, 6][1, 8, 8]
Non-inverted[4][3][2][1][0]
DCI0:LVDSBIAS[0, 3, 44][0, 2, 45][0, 3, 45][0, 2, 46][0, 3, 46][0, 2, 47][0, 3, 47][0, 2, 48][0, 3, 48]
DCI1:LVDSBIAS[1, 13, 7][1, 13, 11][1, 13, 9][1, 12, 9][1, 12, 11][1, 12, 10][1, 12, 7][1, 12, 6][1, 12, 8]
Non-inverted[8][7][6][5][4][3][2][1][0]
MISC:HSWAPENPIN[1, 6, 8][1, 6, 10]
MISC:TDIPIN[1, 6, 6][1, 6, 7]
PULLUP00
PULLDOWN01
PULLNONE10
MISC:PROGPIN[1, 6, 11]
PULLUP0
PULLNONE1

UL.V2P

This tile is used on Virtex 2 Pro.

UL.V2P bittile 0
RowColumn
0123
0 ----
1 ----
2 ----
3 ----
4 ----
5 ----
6 ----
7 ----
8 ----
9 ----
10 ----
11 ----
12 ----
13 ----
14 ----
15 ----
16 ----
17 ----
18 ----
19 ----
20 ----
21 ----
22 ----
23 ----
24 ----
25 ----
26 ----
27 ----
28 ----
29 ----
30 ----
31 --DCI0:TEST_ENABLEDCI0:FORCE_DONE_HIGH
32 --DCI0:PMASK_TERM_SPLIT[4]DCI0:PMASK_TERM_SPLIT[3]
33 --DCI0:PMASK_TERM_SPLIT[2]DCI0:PMASK_TERM_SPLIT[1]
34 --DCI0:PMASK_TERM_SPLIT[0]DCI0:PMASK_TERM_VCC[4]
35 --DCI0:PMASK_TERM_VCC[3]DCI0:PMASK_TERM_VCC[2]
36 --DCI0:PMASK_TERM_VCC[1]DCI0:PMASK_TERM_VCC[0]
37 --DCI0:NMASK_TERM_SPLIT[4]DCI0:NMASK_TERM_SPLIT[3]
38 --DCI0:NMASK_TERM_SPLIT[2]DCI0:NMASK_TERM_SPLIT[1]
39 --DCI0:NMASK_TERM_SPLIT[0]DCI0:QUIET
40 ----
41 ----
42 --DCI0:ENABLE-
43 ----
44 ---DCI0:LVDSBIAS[8]
45 --DCI0:LVDSBIAS[7]DCI0:LVDSBIAS[6]
46 --DCI0:LVDSBIAS[5]DCI0:LVDSBIAS[4]
47 --DCI0:LVDSBIAS[3]DCI0:LVDSBIAS[2]
48 --DCI0:LVDSBIAS[1]DCI0:LVDSBIAS[0]
UL.V2P bittile 1
RowColumn
012345678910111213
0 --------------
1 --------------
2 --------------
3 --------------
4 --------------
5 --------------
6 ------MISC:TDIPIN[1]-DCI1:PMASK_TERM_VCC[1]DCI1:TEST_ENABLE-DCI1:NMASK_TERM_SPLIT[4]DCI1:LVDSBIAS[1]-
7 ------MISC:TDIPIN[0]-DCI1:PMASK_TERM_VCC[2]DCI1:PMASK_TERM_SPLIT[3]DCI1:ENABLEDCI1:NMASK_TERM_SPLIT[1]DCI1:LVDSBIAS[2]DCI1:LVDSBIAS[8]
8 ------MISC:HSWAPENPIN[1]-DCI1:PMASK_TERM_VCC[0]DCI1:FORCE_DONE_HIGH-DCI1:NMASK_TERM_SPLIT[3]DCI1:LVDSBIAS[0]-
9 ------MISC:TEST_LL-DCI1:PMASK_TERM_SPLIT[0]DCI1:PMASK_TERM_SPLIT[1]-DCI1:QUIETDCI1:LVDSBIAS[5]DCI1:LVDSBIAS[6]
10 ------MISC:HSWAPENPIN[0]-DCI1:PMASK_TERM_VCC[4]DCI1:PMASK_TERM_SPLIT[4]-DCI1:NMASK_TERM_SPLIT[2]DCI1:LVDSBIAS[3]-
11 ------MISC:PROGPIN-DCI1:PMASK_TERM_VCC[3]DCI1:PMASK_TERM_SPLIT[2]-DCI1:NMASK_TERM_SPLIT[0]DCI1:LVDSBIAS[4]DCI1:LVDSBIAS[7]
DCI0:ENABLE[0, 2, 42]
DCI0:FORCE_DONE_HIGH[0, 3, 31]
DCI0:QUIET[0, 3, 39]
DCI0:TEST_ENABLE[0, 2, 31]
DCI1:ENABLE[1, 10, 7]
DCI1:FORCE_DONE_HIGH[1, 9, 8]
DCI1:QUIET[1, 11, 9]
DCI1:TEST_ENABLE[1, 9, 6]
MISC:TEST_LL[1, 6, 9]
Non-inverted[0]
DCI0:NMASK_TERM_SPLIT[0, 2, 37][0, 3, 37][0, 2, 38][0, 3, 38][0, 2, 39]
DCI0:PMASK_TERM_SPLIT[0, 2, 32][0, 3, 32][0, 2, 33][0, 3, 33][0, 2, 34]
DCI0:PMASK_TERM_VCC[0, 3, 34][0, 2, 35][0, 3, 35][0, 2, 36][0, 3, 36]
DCI1:NMASK_TERM_SPLIT[1, 11, 6][1, 11, 8][1, 11, 10][1, 11, 7][1, 11, 11]
DCI1:PMASK_TERM_SPLIT[1, 9, 10][1, 9, 7][1, 9, 11][1, 9, 9][1, 8, 9]
DCI1:PMASK_TERM_VCC[1, 8, 10][1, 8, 11][1, 8, 7][1, 8, 6][1, 8, 8]
Non-inverted[4][3][2][1][0]
DCI0:LVDSBIAS[0, 3, 44][0, 2, 45][0, 3, 45][0, 2, 46][0, 3, 46][0, 2, 47][0, 3, 47][0, 2, 48][0, 3, 48]
DCI1:LVDSBIAS[1, 13, 7][1, 13, 11][1, 13, 9][1, 12, 9][1, 12, 11][1, 12, 10][1, 12, 7][1, 12, 6][1, 12, 8]
Non-inverted[8][7][6][5][4][3][2][1][0]
MISC:HSWAPENPIN[1, 6, 8][1, 6, 10]
MISC:TDIPIN[1, 6, 6][1, 6, 7]
PULLUP00
PULLDOWN01
PULLNONE10
MISC:PROGPIN[1, 6, 11]
PULLUP0
PULLNONE1

Lower right

Todo

document

LR.V2

This tile is used on Virtex 2.

LR.V2 bittile 0
RowColumn
0123
0 ----
1 ----
2 ----
3 ----
4 --STARTUP:GTS_GSR_ENABLESTARTUP:GWE_SYNC
5 --STARTUP:GTS_SYNCSTARTUP:GSR_SYNC
6 --ICAP:ENABLEMISC:DONEPIN
7 --MISC:POWERDOWNPINMISC:CCLKPIN
8 ----
9 ----
10 ----
11 ----
12 ----
13 ----
14 ----
15 ----
16 ----
17 ----
18 ----
19 ----
20 ----
21 ----
22 ----
23 ----
24 ----
25 ----
26 ----
27 ----
28 ----
29 ----
30 ----
31 --DCI0:TEST_ENABLEDCI0:FORCE_DONE_HIGH
32 --DCI0:PMASK_TERM_SPLIT[4]DCI0:PMASK_TERM_SPLIT[3]
33 --DCI0:PMASK_TERM_SPLIT[2]DCI0:PMASK_TERM_SPLIT[1]
34 --DCI0:PMASK_TERM_SPLIT[0]DCI0:PMASK_TERM_VCC[4]
35 --DCI0:PMASK_TERM_VCC[3]DCI0:PMASK_TERM_VCC[2]
36 --DCI0:PMASK_TERM_VCC[1]DCI0:PMASK_TERM_VCC[0]
37 --DCI0:NMASK_TERM_SPLIT[4]DCI0:NMASK_TERM_SPLIT[3]
38 --DCI0:NMASK_TERM_SPLIT[2]DCI0:NMASK_TERM_SPLIT[1]
39 --DCI0:NMASK_TERM_SPLIT[0]-
40 ----
41 ----
42 --DCI0:ENABLE-
43 ----
44 ---DCI0:LVDSBIAS[8]
45 --DCI0:LVDSBIAS[7]DCI0:LVDSBIAS[6]
46 --DCI0:LVDSBIAS[5]DCI0:LVDSBIAS[4]
47 --DCI0:LVDSBIAS[3]DCI0:LVDSBIAS[2]
48 --DCI0:LVDSBIAS[1]DCI0:LVDSBIAS[0]
LR.V2 bittile 1
RowColumn
012345678910111213
0 --------------
1 --------------
2 --------------
3 --------------
4 --------------
5 --------------
6 --------DCI1:PMASK_TERM_VCC[1]DCI1:TEST_ENABLE-DCI1:NMASK_TERM_SPLIT[4]DCI1:LVDSBIAS[1]-
7 --------DCI1:PMASK_TERM_VCC[2]DCI1:PMASK_TERM_SPLIT[3]DCI1:ENABLEDCI1:NMASK_TERM_SPLIT[1]DCI1:LVDSBIAS[2]DCI1:LVDSBIAS[8]
8 --------DCI1:PMASK_TERM_VCC[0]DCI1:FORCE_DONE_HIGH-DCI1:NMASK_TERM_SPLIT[3]DCI1:LVDSBIAS[0]-
9 --------DCI1:PMASK_TERM_SPLIT[0]DCI1:PMASK_TERM_SPLIT[1]--DCI1:LVDSBIAS[5]DCI1:LVDSBIAS[6]
10 --------DCI1:PMASK_TERM_VCC[4]DCI1:PMASK_TERM_SPLIT[4]-DCI1:NMASK_TERM_SPLIT[2]DCI1:LVDSBIAS[3]-
11 --------DCI1:PMASK_TERM_VCC[3]DCI1:PMASK_TERM_SPLIT[2]-DCI1:NMASK_TERM_SPLIT[0]DCI1:LVDSBIAS[4]DCI1:LVDSBIAS[7]
DCI0:ENABLE[0, 2, 42]
DCI0:FORCE_DONE_HIGH[0, 3, 31]
DCI0:TEST_ENABLE[0, 2, 31]
DCI1:ENABLE[1, 10, 7]
DCI1:FORCE_DONE_HIGH[1, 9, 8]
DCI1:TEST_ENABLE[1, 9, 6]
ICAP:ENABLE[0, 2, 6]
STARTUP:GSR_SYNC[0, 3, 5]
STARTUP:GTS_GSR_ENABLE[0, 2, 4]
STARTUP:GTS_SYNC[0, 2, 5]
STARTUP:GWE_SYNC[0, 3, 4]
Non-inverted[0]
MISC:CCLKPIN[0, 3, 7]
MISC:DONEPIN[0, 3, 6]
MISC:POWERDOWNPIN[0, 2, 7]
PULLUP0
PULLNONE1
DCI0:NMASK_TERM_SPLIT[0, 2, 37][0, 3, 37][0, 2, 38][0, 3, 38][0, 2, 39]
DCI0:PMASK_TERM_SPLIT[0, 2, 32][0, 3, 32][0, 2, 33][0, 3, 33][0, 2, 34]
DCI0:PMASK_TERM_VCC[0, 3, 34][0, 2, 35][0, 3, 35][0, 2, 36][0, 3, 36]
DCI1:NMASK_TERM_SPLIT[1, 11, 6][1, 11, 8][1, 11, 10][1, 11, 7][1, 11, 11]
DCI1:PMASK_TERM_SPLIT[1, 9, 10][1, 9, 7][1, 9, 11][1, 9, 9][1, 8, 9]
DCI1:PMASK_TERM_VCC[1, 8, 10][1, 8, 11][1, 8, 7][1, 8, 6][1, 8, 8]
Non-inverted[4][3][2][1][0]
DCI0:LVDSBIAS[0, 3, 44][0, 2, 45][0, 3, 45][0, 2, 46][0, 3, 46][0, 2, 47][0, 3, 47][0, 2, 48][0, 3, 48]
DCI1:LVDSBIAS[1, 13, 7][1, 13, 11][1, 13, 9][1, 12, 9][1, 12, 11][1, 12, 10][1, 12, 7][1, 12, 6][1, 12, 8]
Non-inverted[8][7][6][5][4][3][2][1][0]

LR.V2P

This tile is used on Virtex 2 Pro.

LR.V2P bittile 0
RowColumn
0123
0 ----
1 ----
2 ----
3 ----
4 --STARTUP:GTS_GSR_ENABLESTARTUP:GWE_SYNC
5 --STARTUP:GTS_SYNCSTARTUP:GSR_SYNC
6 --ICAP:ENABLEMISC:DONEPIN
7 --MISC:POWERDOWNPINMISC:CCLKPIN
8 ----
9 ----
10 ----
11 ----
12 ----
13 ----
14 ----
15 ----
16 ----
17 ----
18 ----
19 ----
20 ----
21 ----
22 ----
23 ----
24 ----
25 ----
26 ----
27 ----
28 ----
29 ----
30 ----
31 --DCI0:TEST_ENABLEDCI0:FORCE_DONE_HIGH
32 --DCI0:PMASK_TERM_SPLIT[4]DCI0:PMASK_TERM_SPLIT[3]
33 --DCI0:PMASK_TERM_SPLIT[2]DCI0:PMASK_TERM_SPLIT[1]
34 --DCI0:PMASK_TERM_SPLIT[0]DCI0:PMASK_TERM_VCC[4]
35 --DCI0:PMASK_TERM_VCC[3]DCI0:PMASK_TERM_VCC[2]
36 --DCI0:PMASK_TERM_VCC[1]DCI0:PMASK_TERM_VCC[0]
37 --DCI0:NMASK_TERM_SPLIT[4]DCI0:NMASK_TERM_SPLIT[3]
38 --DCI0:NMASK_TERM_SPLIT[2]DCI0:NMASK_TERM_SPLIT[1]
39 --DCI0:NMASK_TERM_SPLIT[0]DCI0:QUIET
40 ----
41 ----
42 --DCI0:ENABLE-
43 ----
44 ---DCI0:LVDSBIAS[8]
45 --DCI0:LVDSBIAS[7]DCI0:LVDSBIAS[6]
46 --DCI0:LVDSBIAS[5]DCI0:LVDSBIAS[4]
47 --DCI0:LVDSBIAS[3]DCI0:LVDSBIAS[2]
48 --DCI0:LVDSBIAS[1]DCI0:LVDSBIAS[0]
LR.V2P bittile 1
RowColumn
012345678910111213
0 --------------
1 --------------
2 --------------
3 --------------
4 --------------
5 --------------
6 --------DCI1:PMASK_TERM_VCC[1]DCI1:TEST_ENABLE-DCI1:NMASK_TERM_SPLIT[4]DCI1:LVDSBIAS[1]-
7 --------DCI1:PMASK_TERM_VCC[2]DCI1:PMASK_TERM_SPLIT[3]DCI1:ENABLEDCI1:NMASK_TERM_SPLIT[1]DCI1:LVDSBIAS[2]DCI1:LVDSBIAS[8]
8 --------DCI1:PMASK_TERM_VCC[0]DCI1:FORCE_DONE_HIGH-DCI1:NMASK_TERM_SPLIT[3]DCI1:LVDSBIAS[0]-
9 --------DCI1:PMASK_TERM_SPLIT[0]DCI1:PMASK_TERM_SPLIT[1]-DCI1:QUIETDCI1:LVDSBIAS[5]DCI1:LVDSBIAS[6]
10 --------DCI1:PMASK_TERM_VCC[4]DCI1:PMASK_TERM_SPLIT[4]-DCI1:NMASK_TERM_SPLIT[2]DCI1:LVDSBIAS[3]-
11 --------DCI1:PMASK_TERM_VCC[3]DCI1:PMASK_TERM_SPLIT[2]-DCI1:NMASK_TERM_SPLIT[0]DCI1:LVDSBIAS[4]DCI1:LVDSBIAS[7]
DCI0:ENABLE[0, 2, 42]
DCI0:FORCE_DONE_HIGH[0, 3, 31]
DCI0:QUIET[0, 3, 39]
DCI0:TEST_ENABLE[0, 2, 31]
DCI1:ENABLE[1, 10, 7]
DCI1:FORCE_DONE_HIGH[1, 9, 8]
DCI1:QUIET[1, 11, 9]
DCI1:TEST_ENABLE[1, 9, 6]
ICAP:ENABLE[0, 2, 6]
STARTUP:GSR_SYNC[0, 3, 5]
STARTUP:GTS_GSR_ENABLE[0, 2, 4]
STARTUP:GTS_SYNC[0, 2, 5]
STARTUP:GWE_SYNC[0, 3, 4]
Non-inverted[0]
MISC:CCLKPIN[0, 3, 7]
MISC:DONEPIN[0, 3, 6]
MISC:POWERDOWNPIN[0, 2, 7]
PULLUP0
PULLNONE1
DCI0:NMASK_TERM_SPLIT[0, 2, 37][0, 3, 37][0, 2, 38][0, 3, 38][0, 2, 39]
DCI0:PMASK_TERM_SPLIT[0, 2, 32][0, 3, 32][0, 2, 33][0, 3, 33][0, 2, 34]
DCI0:PMASK_TERM_VCC[0, 3, 34][0, 2, 35][0, 3, 35][0, 2, 36][0, 3, 36]
DCI1:NMASK_TERM_SPLIT[1, 11, 6][1, 11, 8][1, 11, 10][1, 11, 7][1, 11, 11]
DCI1:PMASK_TERM_SPLIT[1, 9, 10][1, 9, 7][1, 9, 11][1, 9, 9][1, 8, 9]
DCI1:PMASK_TERM_VCC[1, 8, 10][1, 8, 11][1, 8, 7][1, 8, 6][1, 8, 8]
Non-inverted[4][3][2][1][0]
DCI0:LVDSBIAS[0, 3, 44][0, 2, 45][0, 3, 45][0, 2, 46][0, 3, 46][0, 2, 47][0, 3, 47][0, 2, 48][0, 3, 48]
DCI1:LVDSBIAS[1, 13, 7][1, 13, 11][1, 13, 9][1, 12, 9][1, 12, 11][1, 12, 10][1, 12, 7][1, 12, 6][1, 12, 8]
Non-inverted[8][7][6][5][4][3][2][1][0]

Upper right

Todo

document

UR.V2

This tile is used on Virtex 2.

UR.V2 bittile 0
RowColumn
0123
0 ----
1 ----
2 ----
3 ----
4 --~BSCAN:USERID[0]~BSCAN:USERID[1]
5 --~BSCAN:USERID[2]~BSCAN:USERID[3]
6 --~BSCAN:USERID[4]~BSCAN:USERID[5]
7 --~BSCAN:USERID[6]~BSCAN:USERID[7]
8 --~BSCAN:USERID[8]~BSCAN:USERID[9]
9 --~BSCAN:USERID[10]~BSCAN:USERID[11]
10 --~BSCAN:USERID[12]~BSCAN:USERID[13]
11 --~BSCAN:USERID[14]~BSCAN:USERID[15]
12 --~BSCAN:USERID[16]~BSCAN:USERID[17]
13 --~BSCAN:USERID[18]~BSCAN:USERID[19]
14 --~BSCAN:USERID[20]~BSCAN:USERID[21]
15 --~BSCAN:USERID[22]~BSCAN:USERID[23]
16 --~BSCAN:USERID[24]~BSCAN:USERID[25]
17 --~BSCAN:USERID[26]~BSCAN:USERID[27]
18 --~BSCAN:USERID[28]~BSCAN:USERID[29]
19 --~BSCAN:USERID[30]~BSCAN:USERID[31]
20 --BSCAN:TDO_ENABLE[0]BSCAN:TDO_ENABLE[1]
21 ----
22 ----
23 ----
24 ----
25 ----
26 ----
27 ----
28 ----
29 ----
30 ----
31 --DCI0:TEST_ENABLEDCI0:FORCE_DONE_HIGH
32 --DCI0:PMASK_TERM_SPLIT[4]DCI0:PMASK_TERM_SPLIT[3]
33 --DCI0:PMASK_TERM_SPLIT[2]DCI0:PMASK_TERM_SPLIT[1]
34 --DCI0:PMASK_TERM_SPLIT[0]DCI0:PMASK_TERM_VCC[4]
35 --DCI0:PMASK_TERM_VCC[3]DCI0:PMASK_TERM_VCC[2]
36 --DCI0:PMASK_TERM_VCC[1]DCI0:PMASK_TERM_VCC[0]
37 --DCI0:NMASK_TERM_SPLIT[4]DCI0:NMASK_TERM_SPLIT[3]
38 --DCI0:NMASK_TERM_SPLIT[2]DCI0:NMASK_TERM_SPLIT[1]
39 --DCI0:NMASK_TERM_SPLIT[0]-
40 ----
41 ----
42 --DCI0:ENABLE-
43 ----
44 ---DCI0:LVDSBIAS[8]
45 --DCI0:LVDSBIAS[7]DCI0:LVDSBIAS[6]
46 --DCI0:LVDSBIAS[5]DCI0:LVDSBIAS[4]
47 --DCI0:LVDSBIAS[3]DCI0:LVDSBIAS[2]
48 --DCI0:LVDSBIAS[1]DCI0:LVDSBIAS[0]
UR.V2 bittile 1
RowColumn
012345678910111213
0 --------------
1 --------------
2 --------------
3 --------------
4 --------------
5 --------------
6 ---MISC:TMSPIN[1]----DCI1:PMASK_TERM_VCC[1]DCI1:TEST_ENABLE-DCI1:NMASK_TERM_SPLIT[4]DCI1:LVDSBIAS[1]-
7 ---MISC:TCKPIN[1]----DCI1:PMASK_TERM_VCC[2]DCI1:PMASK_TERM_SPLIT[3]DCI1:ENABLEDCI1:NMASK_TERM_SPLIT[1]DCI1:LVDSBIAS[2]DCI1:LVDSBIAS[8]
8 ---MISC:TMSPIN[0]----DCI1:PMASK_TERM_VCC[0]DCI1:FORCE_DONE_HIGH-DCI1:NMASK_TERM_SPLIT[3]DCI1:LVDSBIAS[0]-
9 ---MISC:TDOPIN[1]--MISC:TEST_LL-DCI1:PMASK_TERM_SPLIT[0]DCI1:PMASK_TERM_SPLIT[1]--DCI1:LVDSBIAS[5]DCI1:LVDSBIAS[6]
10 ---MISC:TCKPIN[0]----DCI1:PMASK_TERM_VCC[4]DCI1:PMASK_TERM_SPLIT[4]-DCI1:NMASK_TERM_SPLIT[2]DCI1:LVDSBIAS[3]-
11 ---MISC:TDOPIN[0]----DCI1:PMASK_TERM_VCC[3]DCI1:PMASK_TERM_SPLIT[2]-DCI1:NMASK_TERM_SPLIT[0]DCI1:LVDSBIAS[4]DCI1:LVDSBIAS[7]
BSCAN:USERID[0, 3, 19][0, 2, 19][0, 3, 18][0, 2, 18][0, 3, 17][0, 2, 17][0, 3, 16][0, 2, 16][0, 3, 15][0, 2, 15][0, 3, 14][0, 2, 14][0, 3, 13][0, 2, 13][0, 3, 12][0, 2, 12][0, 3, 11][0, 2, 11][0, 3, 10][0, 2, 10][0, 3, 9][0, 2, 9][0, 3, 8][0, 2, 8][0, 3, 7][0, 2, 7][0, 3, 6][0, 2, 6][0, 3, 5][0, 2, 5][0, 3, 4][0, 2, 4]
Inverted~[31]~[30]~[29]~[28]~[27]~[26]~[25]~[24]~[23]~[22]~[21]~[20]~[19]~[18]~[17]~[16]~[15]~[14]~[13]~[12]~[11]~[10]~[9]~[8]~[7]~[6]~[5]~[4]~[3]~[2]~[1]~[0]
BSCAN:TDO_ENABLE[0, 3, 20][0, 2, 20]
Non-inverted[1][0]
DCI0:ENABLE[0, 2, 42]
DCI0:FORCE_DONE_HIGH[0, 3, 31]
DCI0:TEST_ENABLE[0, 2, 31]
DCI1:ENABLE[1, 10, 7]
DCI1:FORCE_DONE_HIGH[1, 9, 8]
DCI1:TEST_ENABLE[1, 9, 6]
MISC:TEST_LL[1, 6, 9]
Non-inverted[0]
DCI0:NMASK_TERM_SPLIT[0, 2, 37][0, 3, 37][0, 2, 38][0, 3, 38][0, 2, 39]
DCI0:PMASK_TERM_SPLIT[0, 2, 32][0, 3, 32][0, 2, 33][0, 3, 33][0, 2, 34]
DCI0:PMASK_TERM_VCC[0, 3, 34][0, 2, 35][0, 3, 35][0, 2, 36][0, 3, 36]
DCI1:NMASK_TERM_SPLIT[1, 11, 6][1, 11, 8][1, 11, 10][1, 11, 7][1, 11, 11]
DCI1:PMASK_TERM_SPLIT[1, 9, 10][1, 9, 7][1, 9, 11][1, 9, 9][1, 8, 9]
DCI1:PMASK_TERM_VCC[1, 8, 10][1, 8, 11][1, 8, 7][1, 8, 6][1, 8, 8]
Non-inverted[4][3][2][1][0]
DCI0:LVDSBIAS[0, 3, 44][0, 2, 45][0, 3, 45][0, 2, 46][0, 3, 46][0, 2, 47][0, 3, 47][0, 2, 48][0, 3, 48]
DCI1:LVDSBIAS[1, 13, 7][1, 13, 11][1, 13, 9][1, 12, 9][1, 12, 11][1, 12, 10][1, 12, 7][1, 12, 6][1, 12, 8]
Non-inverted[8][7][6][5][4][3][2][1][0]
MISC:TCKPIN[1, 3, 7][1, 3, 10]
MISC:TDOPIN[1, 3, 9][1, 3, 11]
MISC:TMSPIN[1, 3, 6][1, 3, 8]
PULLUP00
PULLDOWN01
PULLNONE10

UR.V2P

This tile is used on Virtex 2 Pro.

UR.V2P bittile 0
RowColumn
0123
0 ----
1 ----
2 ----
3 ----
4 --~BSCAN:USERID[0]~BSCAN:USERID[1]
5 --~BSCAN:USERID[2]~BSCAN:USERID[3]
6 --~BSCAN:USERID[4]~BSCAN:USERID[5]
7 --~BSCAN:USERID[6]~BSCAN:USERID[7]
8 --~BSCAN:USERID[8]~BSCAN:USERID[9]
9 --~BSCAN:USERID[10]~BSCAN:USERID[11]
10 --~BSCAN:USERID[12]~BSCAN:USERID[13]
11 --~BSCAN:USERID[14]~BSCAN:USERID[15]
12 --~BSCAN:USERID[16]~BSCAN:USERID[17]
13 --~BSCAN:USERID[18]~BSCAN:USERID[19]
14 --~BSCAN:USERID[20]~BSCAN:USERID[21]
15 --~BSCAN:USERID[22]~BSCAN:USERID[23]
16 --~BSCAN:USERID[24]~BSCAN:USERID[25]
17 --~BSCAN:USERID[26]~BSCAN:USERID[27]
18 --~BSCAN:USERID[28]~BSCAN:USERID[29]
19 --~BSCAN:USERID[30]~BSCAN:USERID[31]
20 --BSCAN:TDO_ENABLE[0]BSCAN:TDO_ENABLE[1]
21 ----
22 ----
23 ----
24 ----
25 ----
26 ----
27 ----
28 ----
29 ----
30 ----
31 --DCI0:TEST_ENABLEDCI0:FORCE_DONE_HIGH
32 --DCI0:PMASK_TERM_SPLIT[4]DCI0:PMASK_TERM_SPLIT[3]
33 --DCI0:PMASK_TERM_SPLIT[2]DCI0:PMASK_TERM_SPLIT[1]
34 --DCI0:PMASK_TERM_SPLIT[0]DCI0:PMASK_TERM_VCC[4]
35 --DCI0:PMASK_TERM_VCC[3]DCI0:PMASK_TERM_VCC[2]
36 --DCI0:PMASK_TERM_VCC[1]DCI0:PMASK_TERM_VCC[0]
37 --DCI0:NMASK_TERM_SPLIT[4]DCI0:NMASK_TERM_SPLIT[3]
38 --DCI0:NMASK_TERM_SPLIT[2]DCI0:NMASK_TERM_SPLIT[1]
39 --DCI0:NMASK_TERM_SPLIT[0]DCI0:QUIET
40 ----
41 ----
42 --DCI0:ENABLEJTAGPPC:ENABLE
43 ----
44 ---DCI0:LVDSBIAS[8]
45 --DCI0:LVDSBIAS[7]DCI0:LVDSBIAS[6]
46 --DCI0:LVDSBIAS[5]DCI0:LVDSBIAS[4]
47 --DCI0:LVDSBIAS[3]DCI0:LVDSBIAS[2]
48 --DCI0:LVDSBIAS[1]DCI0:LVDSBIAS[0]
UR.V2P bittile 1
RowColumn
012345678910111213
0 --------------
1 --------------
2 --------------
3 --------------
4 --------------
5 --------------
6 ---MISC:TMSPIN[1]----DCI1:PMASK_TERM_VCC[1]DCI1:TEST_ENABLE-DCI1:NMASK_TERM_SPLIT[4]DCI1:LVDSBIAS[1]-
7 ---MISC:TCKPIN[1]----DCI1:PMASK_TERM_VCC[2]DCI1:PMASK_TERM_SPLIT[3]DCI1:ENABLEDCI1:NMASK_TERM_SPLIT[1]DCI1:LVDSBIAS[2]DCI1:LVDSBIAS[8]
8 ---MISC:TMSPIN[0]----DCI1:PMASK_TERM_VCC[0]DCI1:FORCE_DONE_HIGH-DCI1:NMASK_TERM_SPLIT[3]DCI1:LVDSBIAS[0]-
9 ---MISC:TDOPIN[1]--MISC:TEST_LL-DCI1:PMASK_TERM_SPLIT[0]DCI1:PMASK_TERM_SPLIT[1]-DCI1:QUIETDCI1:LVDSBIAS[5]DCI1:LVDSBIAS[6]
10 ---MISC:TCKPIN[0]----DCI1:PMASK_TERM_VCC[4]DCI1:PMASK_TERM_SPLIT[4]-DCI1:NMASK_TERM_SPLIT[2]DCI1:LVDSBIAS[3]-
11 ---MISC:TDOPIN[0]----DCI1:PMASK_TERM_VCC[3]DCI1:PMASK_TERM_SPLIT[2]-DCI1:NMASK_TERM_SPLIT[0]DCI1:LVDSBIAS[4]DCI1:LVDSBIAS[7]
BSCAN:USERID[0, 3, 19][0, 2, 19][0, 3, 18][0, 2, 18][0, 3, 17][0, 2, 17][0, 3, 16][0, 2, 16][0, 3, 15][0, 2, 15][0, 3, 14][0, 2, 14][0, 3, 13][0, 2, 13][0, 3, 12][0, 2, 12][0, 3, 11][0, 2, 11][0, 3, 10][0, 2, 10][0, 3, 9][0, 2, 9][0, 3, 8][0, 2, 8][0, 3, 7][0, 2, 7][0, 3, 6][0, 2, 6][0, 3, 5][0, 2, 5][0, 3, 4][0, 2, 4]
Inverted~[31]~[30]~[29]~[28]~[27]~[26]~[25]~[24]~[23]~[22]~[21]~[20]~[19]~[18]~[17]~[16]~[15]~[14]~[13]~[12]~[11]~[10]~[9]~[8]~[7]~[6]~[5]~[4]~[3]~[2]~[1]~[0]
BSCAN:TDO_ENABLE[0, 3, 20][0, 2, 20]
Non-inverted[1][0]
DCI0:ENABLE[0, 2, 42]
DCI0:FORCE_DONE_HIGH[0, 3, 31]
DCI0:QUIET[0, 3, 39]
DCI0:TEST_ENABLE[0, 2, 31]
DCI1:ENABLE[1, 10, 7]
DCI1:FORCE_DONE_HIGH[1, 9, 8]
DCI1:QUIET[1, 11, 9]
DCI1:TEST_ENABLE[1, 9, 6]
JTAGPPC:ENABLE[0, 3, 42]
MISC:TEST_LL[1, 6, 9]
Non-inverted[0]
DCI0:NMASK_TERM_SPLIT[0, 2, 37][0, 3, 37][0, 2, 38][0, 3, 38][0, 2, 39]
DCI0:PMASK_TERM_SPLIT[0, 2, 32][0, 3, 32][0, 2, 33][0, 3, 33][0, 2, 34]
DCI0:PMASK_TERM_VCC[0, 3, 34][0, 2, 35][0, 3, 35][0, 2, 36][0, 3, 36]
DCI1:NMASK_TERM_SPLIT[1, 11, 6][1, 11, 8][1, 11, 10][1, 11, 7][1, 11, 11]
DCI1:PMASK_TERM_SPLIT[1, 9, 10][1, 9, 7][1, 9, 11][1, 9, 9][1, 8, 9]
DCI1:PMASK_TERM_VCC[1, 8, 10][1, 8, 11][1, 8, 7][1, 8, 6][1, 8, 8]
Non-inverted[4][3][2][1][0]
DCI0:LVDSBIAS[0, 3, 44][0, 2, 45][0, 3, 45][0, 2, 46][0, 3, 46][0, 2, 47][0, 3, 47][0, 2, 48][0, 3, 48]
DCI1:LVDSBIAS[1, 13, 7][1, 13, 11][1, 13, 9][1, 12, 9][1, 12, 11][1, 12, 10][1, 12, 7][1, 12, 6][1, 12, 8]
Non-inverted[8][7][6][5][4][3][2][1][0]
MISC:TCKPIN[1, 3, 7][1, 3, 10]
MISC:TDOPIN[1, 3, 9][1, 3, 11]
MISC:TMSPIN[1, 3, 6][1, 3, 8]
PULLUP00
PULLDOWN01
PULLNONE10

I/O data — Virtex 2

NameIOSTD:V2:LVDSBIAS
[8][7][6][5][4][3][2][1][0]
LDT_25001000001
LVDSEXT_25001000001
LVDSEXT_25_DCI001000001
LVDSEXT_33001010001
LVDSEXT_33_DCI001010001
LVDS_25001000001
LVDS_25_DCI001000001
LVDS_33001010001
LVDS_33_DCI001010001
OFF000000000
ULVDS_25001000001
NameIOSTD:V2:PMASK_TERM_SPLITIOSTD:V2:NMASK_TERM_SPLIT
[4][3][2][1][0][4][3][2][1][0]
HSTL_II_DCI1110110010
HSTL_II_DCI_181110110010
HSTL_I_DCI0000000000
HSTL_I_DCI_180000000000
LVDSEXT_25_DCI0000000000
LVDSEXT_33_DCI0000000000
LVDS_25_DCI0000000000
LVDS_33_DCI0000000000
OFF0000000000
SSTL18_II_DCI0000000000
SSTL18_I_DCI0000000000
SSTL2_II_DCI0010000100
SSTL2_I_DCI0000000000
SSTL3_II_DCI1100010000
SSTL3_I_DCI0000000000
NameIOSTD:V2:PMASK_TERM_VCC
[4][3][2][1][0]
GTLP_DCI00000
GTL_DCI00000
HSTL_III_DCI00000
HSTL_III_DCI_1800000
HSTL_IV_DCI00001
HSTL_IV_DCI_1800001
OFF00000

I/O data — Virtex 2 Pro

NameIOSTD:V2P:LVDSBIAS
[8][7][6][5][4][3][2][1][0]
LDT_25000100001
LVDSEXT_25000100001
LVDSEXT_25_DCI000100001
LVDS_25000100001
LVDS_25_DCI000100001
OFF000000000
ULVDS_25000100001
NameIOSTD:V2P:PMASK_TERM_SPLITIOSTD:V2P:NMASK_TERM_SPLIT
[4][3][2][1][0][4][3][2][1][0]
HSTL_II_DCI1110100010
HSTL_II_DCI_181110100010
HSTL_I_DCI0000000000
HSTL_I_DCI_180000000000
LVDSEXT_25_DCI0000000000
LVDS_25_DCI0000000000
OFF0000000000
SSTL18_II_DCI0010010100
SSTL18_I_DCI0000000000
SSTL2_II_DCI0000010100
SSTL2_I_DCI0000000000
NameIOSTD:V2P:PMASK_TERM_VCC
[4][3][2][1][0]
GTLP_DCI00000
GTL_DCI00000
HSTL_III_DCI00000
HSTL_III_DCI_1800000
HSTL_IV_DCI00100
HSTL_IV_DCI_1800100
OFF00000