Input / Output
Todo
document
I/O interface
Todo
document
IOI
IOI0:IFF1_INIT | [0, 1, 9] |
---|---|
IOI0:IFF1_SRVAL | [0, 0, 2] |
IOI0:IFF2_INIT | [0, 1, 13] |
IOI0:IFF2_SRVAL | [0, 0, 20] |
IOI0:INV.ICE | [0, 3, 6] |
IOI0:INV.ICLK1 | [0, 3, 8] |
IOI0:INV.ICLK2 | [0, 3, 0] |
IOI0:INV.OTCLK1 | [0, 3, 19] |
IOI0:INV.OTCLK2 | [0, 3, 9] |
IOI0:INV.REV | [0, 3, 2] |
IOI0:INV.TCE | [0, 3, 4] |
IOI0:OFF1_SRVAL | [0, 3, 1] |
IOI0:OFF2_SRVAL | [0, 3, 18] |
IOI0:OFF_INIT | [0, 2, 17] |
IOI0:TFF1_SRVAL | [0, 0, 5] |
IOI0:TFF2_SRVAL | [0, 0, 19] |
IOI0:TFF_INIT | [0, 1, 17] |
IOI1:IFF1_INIT | [0, 1, 29] |
IOI1:IFF1_SRVAL | [0, 0, 21] |
IOI1:IFF2_INIT | [0, 1, 33] |
IOI1:IFF2_SRVAL | [0, 0, 39] |
IOI1:INV.ICE | [0, 3, 26] |
IOI1:INV.ICLK1 | [0, 3, 28] |
IOI1:INV.ICLK2 | [0, 3, 20] |
IOI1:INV.OTCLK1 | [0, 3, 39] |
IOI1:INV.OTCLK2 | [0, 3, 29] |
IOI1:INV.REV | [0, 3, 22] |
IOI1:INV.TCE | [0, 3, 24] |
IOI1:OFF1_SRVAL | [0, 3, 21] |
IOI1:OFF2_SRVAL | [0, 3, 38] |
IOI1:OFF_INIT | [0, 2, 37] |
IOI1:TFF1_SRVAL | [0, 0, 22] |
IOI1:TFF2_SRVAL | [0, 0, 38] |
IOI1:TFF_INIT | [0, 1, 37] |
IOI2:IFF1_INIT | [0, 1, 49] |
IOI2:IFF1_SRVAL | [0, 0, 40] |
IOI2:IFF2_INIT | [0, 1, 53] |
IOI2:IFF2_SRVAL | [0, 0, 58] |
IOI2:INV.ICE | [0, 3, 46] |
IOI2:INV.ICLK1 | [0, 3, 48] |
IOI2:INV.ICLK2 | [0, 3, 40] |
IOI2:INV.OTCLK1 | [0, 3, 59] |
IOI2:INV.OTCLK2 | [0, 3, 49] |
IOI2:INV.REV | [0, 3, 42] |
IOI2:INV.TCE | [0, 3, 44] |
IOI2:OFF1_SRVAL | [0, 3, 41] |
IOI2:OFF2_SRVAL | [0, 3, 58] |
IOI2:OFF_INIT | [0, 2, 55] |
IOI2:TFF1_SRVAL | [0, 0, 42] |
IOI2:TFF2_SRVAL | [0, 0, 57] |
IOI2:TFF_INIT | [0, 1, 55] |
IOI3:IFF1_INIT | [0, 1, 69] |
IOI3:IFF1_SRVAL | [0, 0, 59] |
IOI3:IFF2_INIT | [0, 1, 73] |
IOI3:IFF2_SRVAL | [0, 0, 77] |
IOI3:INV.ICE | [0, 3, 66] |
IOI3:INV.ICLK1 | [0, 3, 68] |
IOI3:INV.ICLK2 | [0, 3, 60] |
IOI3:INV.OTCLK1 | [0, 3, 79] |
IOI3:INV.OTCLK2 | [0, 3, 69] |
IOI3:INV.REV | [0, 3, 62] |
IOI3:INV.TCE | [0, 3, 64] |
IOI3:OFF1_SRVAL | [0, 3, 61] |
IOI3:OFF2_SRVAL | [0, 3, 78] |
IOI3:OFF_INIT | [0, 2, 75] |
IOI3:TFF1_SRVAL | [0, 0, 60] |
IOI3:TFF2_SRVAL | [0, 0, 76] |
IOI3:TFF_INIT | [0, 1, 75] |
Inverted | ~[0] |
IOI0:TSBYPASS_MUX | [0, 0, 3] |
---|---|
IOI1:TSBYPASS_MUX | [0, 0, 23] |
IOI2:TSBYPASS_MUX | [0, 0, 43] |
IOI3:TSBYPASS_MUX | [0, 0, 63] |
TMUX | 0 |
GND | 1 |
IOI0:IFF_DELAY_ENABLE | [0, 0, 11] |
---|---|
IOI0:IFF_LATCH | [0, 0, 16] |
IOI0:IFF_REV_ENABLE | [0, 1, 3] |
IOI0:IFF_SR_ENABLE | [0, 1, 2] |
IOI0:IFF_SR_SYNC | [0, 0, 13] |
IOI0:IFF_TSBYPASS_ENABLE | [0, 0, 9] |
IOI0:INV.O1 | [0, 3, 11] |
IOI0:INV.O2 | [0, 3, 13] |
IOI0:INV.T1 | [0, 3, 15] |
IOI0:INV.T2 | [0, 3, 17] |
IOI0:I_DELAY_ENABLE | [0, 0, 4] |
IOI0:I_TSBYPASS_ENABLE | [0, 0, 6] |
IOI0:OFF1_LATCH | [0, 3, 7] |
IOI0:OFF2_LATCH | [0, 3, 14] |
IOI0:OFF_REV_ENABLE | [0, 2, 4] |
IOI0:OFF_SR_ENABLE | [0, 2, 5] |
IOI0:OFF_SR_SYNC | [0, 0, 10] |
IOI0:READBACK_I | [0, 2, 13] |
IOI0:TFF1_LATCH | [0, 0, 34] |
IOI0:TFF2_LATCH | [0, 0, 17] |
IOI0:TFF_REV_ENABLE | [0, 1, 4] |
IOI0:TFF_SR_ENABLE | [0, 1, 5] |
IOI0:TFF_SR_SYNC | [0, 0, 12] |
IOI1:IFF_DELAY_ENABLE | [0, 0, 31] |
IOI1:IFF_LATCH | [0, 0, 35] |
IOI1:IFF_REV_ENABLE | [0, 1, 22] |
IOI1:IFF_SR_ENABLE | [0, 1, 21] |
IOI1:IFF_SR_SYNC | [0, 0, 32] |
IOI1:IFF_TSBYPASS_ENABLE | [0, 0, 29] |
IOI1:INV.O1 | [0, 3, 31] |
IOI1:INV.O2 | [0, 3, 33] |
IOI1:INV.T1 | [0, 3, 35] |
IOI1:INV.T2 | [0, 3, 37] |
IOI1:I_DELAY_ENABLE | [0, 0, 24] |
IOI1:I_TSBYPASS_ENABLE | [0, 0, 26] |
IOI1:OFF1_LATCH | [0, 3, 27] |
IOI1:OFF2_LATCH | [0, 3, 34] |
IOI1:OFF_REV_ENABLE | [0, 2, 23] |
IOI1:OFF_SR_ENABLE | [0, 2, 24] |
IOI1:OFF_SR_SYNC | [0, 0, 28] |
IOI1:READBACK_I | [0, 2, 33] |
IOI1:TFF1_LATCH | [0, 0, 18] |
IOI1:TFF2_LATCH | [0, 0, 37] |
IOI1:TFF_REV_ENABLE | [0, 1, 23] |
IOI1:TFF_SR_ENABLE | [0, 1, 24] |
IOI1:TFF_SR_SYNC | [0, 0, 30] |
IOI2:IFF_DELAY_ENABLE | [0, 0, 51] |
IOI2:IFF_LATCH | [0, 0, 54] |
IOI2:IFF_REV_ENABLE | [0, 1, 41] |
IOI2:IFF_SR_ENABLE | [0, 1, 40] |
IOI2:IFF_SR_SYNC | [0, 0, 52] |
IOI2:IFF_TSBYPASS_ENABLE | [0, 0, 49] |
IOI2:INV.O1 | [0, 3, 51] |
IOI2:INV.O2 | [0, 3, 53] |
IOI2:INV.T1 | [0, 3, 55] |
IOI2:INV.T2 | [0, 3, 57] |
IOI2:I_DELAY_ENABLE | [0, 0, 44] |
IOI2:I_TSBYPASS_ENABLE | [0, 0, 46] |
IOI2:OFF1_LATCH | [0, 3, 47] |
IOI2:OFF2_LATCH | [0, 3, 54] |
IOI2:OFF_REV_ENABLE | [0, 2, 42] |
IOI2:OFF_SR_ENABLE | [0, 2, 43] |
IOI2:OFF_SR_SYNC | [0, 0, 48] |
IOI2:READBACK_I | [0, 2, 53] |
IOI2:TFF1_LATCH | [0, 0, 41] |
IOI2:TFF2_LATCH | [0, 0, 56] |
IOI2:TFF_REV_ENABLE | [0, 1, 42] |
IOI2:TFF_SR_ENABLE | [0, 1, 43] |
IOI2:TFF_SR_SYNC | [0, 0, 50] |
IOI3:IFF_DELAY_ENABLE | [0, 0, 71] |
IOI3:IFF_LATCH | [0, 0, 73] |
IOI3:IFF_REV_ENABLE | [0, 1, 60] |
IOI3:IFF_SR_ENABLE | [0, 1, 59] |
IOI3:IFF_SR_SYNC | [0, 0, 70] |
IOI3:IFF_TSBYPASS_ENABLE | [0, 0, 69] |
IOI3:INV.O1 | [0, 3, 71] |
IOI3:INV.O2 | [0, 3, 73] |
IOI3:INV.T1 | [0, 3, 75] |
IOI3:INV.T2 | [0, 3, 77] |
IOI3:I_DELAY_ENABLE | [0, 0, 64] |
IOI3:I_TSBYPASS_ENABLE | [0, 0, 66] |
IOI3:OFF1_LATCH | [0, 3, 67] |
IOI3:OFF2_LATCH | [0, 3, 74] |
IOI3:OFF_REV_ENABLE | [0, 2, 61] |
IOI3:OFF_SR_ENABLE | [0, 2, 62] |
IOI3:OFF_SR_SYNC | [0, 0, 67] |
IOI3:READBACK_I | [0, 2, 73] |
IOI3:TFF1_LATCH | [0, 0, 62] |
IOI3:TFF2_LATCH | [0, 0, 75] |
IOI3:TFF_REV_ENABLE | [0, 1, 61] |
IOI3:TFF_SR_ENABLE | [0, 1, 62] |
IOI3:TFF_SR_SYNC | [0, 0, 68] |
Non-inverted | [0] |
IOI0:TMUX | [0, 0, 14] | [0, 0, 8] | [0, 0, 15] | [0, 0, 7] |
---|---|---|---|---|
IOI1:TMUX | [0, 0, 33] | [0, 0, 27] | [0, 0, 36] | [0, 0, 25] |
IOI2:TMUX | [0, 0, 53] | [0, 0, 47] | [0, 0, 55] | [0, 0, 45] |
IOI3:TMUX | [0, 0, 72] | [0, 0, 65] | [0, 0, 74] | [0, 0, 61] |
NONE | 0 | 0 | 0 | 0 |
T1 | 0 | 0 | 0 | 1 |
T2 | 0 | 0 | 1 | 0 |
TFF1 | 0 | 1 | 0 | 0 |
TFF2 | 1 | 0 | 0 | 0 |
TFFDDR | 1 | 1 | 0 | 0 |
IOI0:OMUX | [0, 3, 12] | [0, 3, 3] | [0, 3, 10] | [0, 3, 5] |
---|---|---|---|---|
IOI1:OMUX | [0, 3, 32] | [0, 3, 23] | [0, 3, 30] | [0, 3, 25] |
IOI2:OMUX | [0, 3, 52] | [0, 3, 43] | [0, 3, 50] | [0, 3, 45] |
IOI3:OMUX | [0, 3, 72] | [0, 3, 63] | [0, 3, 70] | [0, 3, 65] |
NONE | 0 | 0 | 0 | 0 |
O1 | 0 | 0 | 0 | 1 |
O2 | 0 | 0 | 1 | 0 |
OFF1 | 0 | 1 | 0 | 0 |
OFF2 | 1 | 0 | 0 | 0 |
OFFDDR | 1 | 1 | 0 | 0 |
IOI.CLK_B
IOI0:IFF1_INIT | [0, 1, 9] |
---|---|
IOI0:IFF1_SRVAL | [0, 0, 2] |
IOI0:IFF2_INIT | [0, 1, 13] |
IOI0:IFF2_SRVAL | [0, 0, 20] |
IOI0:INV.ICE | [0, 3, 6] |
IOI0:INV.ICLK1 | [0, 3, 8] |
IOI0:INV.ICLK2 | [0, 3, 0] |
IOI0:INV.OTCLK1 | [0, 3, 19] |
IOI0:INV.OTCLK2 | [0, 3, 9] |
IOI0:INV.REV | [0, 3, 2] |
IOI0:INV.TCE | [0, 3, 4] |
IOI0:OFF1_SRVAL | [0, 3, 1] |
IOI0:OFF2_SRVAL | [0, 3, 18] |
IOI0:OFF_INIT | [0, 2, 17] |
IOI0:TFF1_SRVAL | [0, 0, 5] |
IOI0:TFF2_SRVAL | [0, 0, 19] |
IOI0:TFF_INIT | [0, 1, 17] |
IOI1:IFF1_INIT | [0, 1, 29] |
IOI1:IFF1_SRVAL | [0, 0, 21] |
IOI1:IFF2_INIT | [0, 1, 33] |
IOI1:IFF2_SRVAL | [0, 0, 39] |
IOI1:INV.ICE | [0, 3, 26] |
IOI1:INV.ICLK1 | [0, 3, 28] |
IOI1:INV.ICLK2 | [0, 3, 20] |
IOI1:INV.OTCLK1 | [0, 3, 39] |
IOI1:INV.OTCLK2 | [0, 3, 29] |
IOI1:INV.REV | [0, 3, 22] |
IOI1:INV.TCE | [0, 3, 24] |
IOI1:OFF1_SRVAL | [0, 3, 21] |
IOI1:OFF2_SRVAL | [0, 3, 38] |
IOI1:OFF_INIT | [0, 2, 37] |
IOI1:TFF1_SRVAL | [0, 0, 22] |
IOI1:TFF2_SRVAL | [0, 0, 38] |
IOI1:TFF_INIT | [0, 1, 37] |
Inverted | ~[0] |
IOI0:TSBYPASS_MUX | [0, 0, 3] |
---|---|
IOI1:TSBYPASS_MUX | [0, 0, 23] |
TMUX | 0 |
GND | 1 |
IOI0:IFF_DELAY_ENABLE | [0, 0, 11] |
---|---|
IOI0:IFF_LATCH | [0, 0, 16] |
IOI0:IFF_REV_ENABLE | [0, 1, 3] |
IOI0:IFF_SR_ENABLE | [0, 1, 2] |
IOI0:IFF_SR_SYNC | [0, 0, 13] |
IOI0:IFF_TSBYPASS_ENABLE | [0, 0, 9] |
IOI0:INV.O1 | [0, 3, 11] |
IOI0:INV.O2 | [0, 3, 13] |
IOI0:INV.T1 | [0, 3, 15] |
IOI0:INV.T2 | [0, 3, 17] |
IOI0:I_DELAY_ENABLE | [0, 0, 4] |
IOI0:I_TSBYPASS_ENABLE | [0, 0, 6] |
IOI0:OFF1_LATCH | [0, 3, 7] |
IOI0:OFF2_LATCH | [0, 3, 14] |
IOI0:OFF_REV_ENABLE | [0, 2, 4] |
IOI0:OFF_SR_ENABLE | [0, 2, 5] |
IOI0:OFF_SR_SYNC | [0, 0, 10] |
IOI0:READBACK_I | [0, 2, 13] |
IOI0:TFF1_LATCH | [0, 0, 34] |
IOI0:TFF2_LATCH | [0, 0, 17] |
IOI0:TFF_REV_ENABLE | [0, 1, 4] |
IOI0:TFF_SR_ENABLE | [0, 1, 5] |
IOI0:TFF_SR_SYNC | [0, 0, 12] |
IOI1:IFF_DELAY_ENABLE | [0, 0, 31] |
IOI1:IFF_LATCH | [0, 0, 35] |
IOI1:IFF_REV_ENABLE | [0, 1, 22] |
IOI1:IFF_SR_ENABLE | [0, 1, 21] |
IOI1:IFF_SR_SYNC | [0, 0, 32] |
IOI1:IFF_TSBYPASS_ENABLE | [0, 0, 29] |
IOI1:INV.O1 | [0, 3, 31] |
IOI1:INV.O2 | [0, 3, 33] |
IOI1:INV.T1 | [0, 3, 35] |
IOI1:INV.T2 | [0, 3, 37] |
IOI1:I_DELAY_ENABLE | [0, 0, 24] |
IOI1:I_TSBYPASS_ENABLE | [0, 0, 26] |
IOI1:OFF1_LATCH | [0, 3, 27] |
IOI1:OFF2_LATCH | [0, 3, 34] |
IOI1:OFF_REV_ENABLE | [0, 2, 23] |
IOI1:OFF_SR_ENABLE | [0, 2, 24] |
IOI1:OFF_SR_SYNC | [0, 0, 28] |
IOI1:READBACK_I | [0, 2, 33] |
IOI1:TFF1_LATCH | [0, 0, 18] |
IOI1:TFF2_LATCH | [0, 0, 37] |
IOI1:TFF_REV_ENABLE | [0, 1, 23] |
IOI1:TFF_SR_ENABLE | [0, 1, 24] |
IOI1:TFF_SR_SYNC | [0, 0, 30] |
Non-inverted | [0] |
IOI0:TMUX | [0, 0, 14] | [0, 0, 8] | [0, 0, 15] | [0, 0, 7] |
---|---|---|---|---|
IOI1:TMUX | [0, 0, 33] | [0, 0, 27] | [0, 0, 36] | [0, 0, 25] |
NONE | 0 | 0 | 0 | 0 |
T1 | 0 | 0 | 0 | 1 |
T2 | 0 | 0 | 1 | 0 |
TFF1 | 0 | 1 | 0 | 0 |
TFF2 | 1 | 0 | 0 | 0 |
TFFDDR | 1 | 1 | 0 | 0 |
IOI0:OMUX | [0, 3, 12] | [0, 3, 3] | [0, 3, 10] | [0, 3, 5] |
---|---|---|---|---|
IOI1:OMUX | [0, 3, 32] | [0, 3, 23] | [0, 3, 30] | [0, 3, 25] |
NONE | 0 | 0 | 0 | 0 |
O1 | 0 | 0 | 0 | 1 |
O2 | 0 | 0 | 1 | 0 |
OFF1 | 0 | 1 | 0 | 0 |
OFF2 | 1 | 0 | 0 | 0 |
OFFDDR | 1 | 1 | 0 | 0 |
IOI.CLK_T
IOI2:IFF1_INIT | [0, 1, 49] |
---|---|
IOI2:IFF1_SRVAL | [0, 0, 40] |
IOI2:IFF2_INIT | [0, 1, 53] |
IOI2:IFF2_SRVAL | [0, 0, 58] |
IOI2:INV.ICE | [0, 3, 46] |
IOI2:INV.ICLK1 | [0, 3, 48] |
IOI2:INV.ICLK2 | [0, 3, 40] |
IOI2:INV.OTCLK1 | [0, 3, 59] |
IOI2:INV.OTCLK2 | [0, 3, 49] |
IOI2:INV.REV | [0, 3, 42] |
IOI2:INV.TCE | [0, 3, 44] |
IOI2:OFF1_SRVAL | [0, 3, 41] |
IOI2:OFF2_SRVAL | [0, 3, 58] |
IOI2:OFF_INIT | [0, 2, 55] |
IOI2:TFF1_SRVAL | [0, 0, 42] |
IOI2:TFF2_SRVAL | [0, 0, 57] |
IOI2:TFF_INIT | [0, 1, 55] |
IOI3:IFF1_INIT | [0, 1, 69] |
IOI3:IFF1_SRVAL | [0, 0, 59] |
IOI3:IFF2_INIT | [0, 1, 73] |
IOI3:IFF2_SRVAL | [0, 0, 77] |
IOI3:INV.ICE | [0, 3, 66] |
IOI3:INV.ICLK1 | [0, 3, 68] |
IOI3:INV.ICLK2 | [0, 3, 60] |
IOI3:INV.OTCLK1 | [0, 3, 79] |
IOI3:INV.OTCLK2 | [0, 3, 69] |
IOI3:INV.REV | [0, 3, 62] |
IOI3:INV.TCE | [0, 3, 64] |
IOI3:OFF1_SRVAL | [0, 3, 61] |
IOI3:OFF2_SRVAL | [0, 3, 78] |
IOI3:OFF_INIT | [0, 2, 75] |
IOI3:TFF1_SRVAL | [0, 0, 60] |
IOI3:TFF2_SRVAL | [0, 0, 76] |
IOI3:TFF_INIT | [0, 1, 75] |
Inverted | ~[0] |
IOI2:IFF_DELAY_ENABLE | [0, 0, 51] |
---|---|
IOI2:IFF_LATCH | [0, 0, 54] |
IOI2:IFF_REV_ENABLE | [0, 1, 41] |
IOI2:IFF_SR_ENABLE | [0, 1, 40] |
IOI2:IFF_SR_SYNC | [0, 0, 52] |
IOI2:IFF_TSBYPASS_ENABLE | [0, 0, 49] |
IOI2:INV.O1 | [0, 3, 51] |
IOI2:INV.O2 | [0, 3, 53] |
IOI2:INV.T1 | [0, 3, 55] |
IOI2:INV.T2 | [0, 3, 57] |
IOI2:I_DELAY_ENABLE | [0, 0, 44] |
IOI2:I_TSBYPASS_ENABLE | [0, 0, 46] |
IOI2:OFF1_LATCH | [0, 3, 47] |
IOI2:OFF2_LATCH | [0, 3, 54] |
IOI2:OFF_REV_ENABLE | [0, 2, 42] |
IOI2:OFF_SR_ENABLE | [0, 2, 43] |
IOI2:OFF_SR_SYNC | [0, 0, 48] |
IOI2:READBACK_I | [0, 2, 53] |
IOI2:TFF1_LATCH | [0, 0, 41] |
IOI2:TFF2_LATCH | [0, 0, 56] |
IOI2:TFF_REV_ENABLE | [0, 1, 42] |
IOI2:TFF_SR_ENABLE | [0, 1, 43] |
IOI2:TFF_SR_SYNC | [0, 0, 50] |
IOI3:IFF_DELAY_ENABLE | [0, 0, 71] |
IOI3:IFF_LATCH | [0, 0, 73] |
IOI3:IFF_REV_ENABLE | [0, 1, 60] |
IOI3:IFF_SR_ENABLE | [0, 1, 59] |
IOI3:IFF_SR_SYNC | [0, 0, 70] |
IOI3:IFF_TSBYPASS_ENABLE | [0, 0, 69] |
IOI3:INV.O1 | [0, 3, 71] |
IOI3:INV.O2 | [0, 3, 73] |
IOI3:INV.T1 | [0, 3, 75] |
IOI3:INV.T2 | [0, 3, 77] |
IOI3:I_DELAY_ENABLE | [0, 0, 64] |
IOI3:I_TSBYPASS_ENABLE | [0, 0, 66] |
IOI3:OFF1_LATCH | [0, 3, 67] |
IOI3:OFF2_LATCH | [0, 3, 74] |
IOI3:OFF_REV_ENABLE | [0, 2, 61] |
IOI3:OFF_SR_ENABLE | [0, 2, 62] |
IOI3:OFF_SR_SYNC | [0, 0, 67] |
IOI3:READBACK_I | [0, 2, 73] |
IOI3:TFF1_LATCH | [0, 0, 62] |
IOI3:TFF2_LATCH | [0, 0, 75] |
IOI3:TFF_REV_ENABLE | [0, 1, 61] |
IOI3:TFF_SR_ENABLE | [0, 1, 62] |
IOI3:TFF_SR_SYNC | [0, 0, 68] |
Non-inverted | [0] |
IOI2:TSBYPASS_MUX | [0, 0, 43] |
---|---|
IOI3:TSBYPASS_MUX | [0, 0, 63] |
TMUX | 0 |
GND | 1 |
IOI2:TMUX | [0, 0, 53] | [0, 0, 47] | [0, 0, 55] | [0, 0, 45] |
---|---|---|---|---|
IOI3:TMUX | [0, 0, 72] | [0, 0, 65] | [0, 0, 74] | [0, 0, 61] |
NONE | 0 | 0 | 0 | 0 |
T1 | 0 | 0 | 0 | 1 |
T2 | 0 | 0 | 1 | 0 |
TFF1 | 0 | 1 | 0 | 0 |
TFF2 | 1 | 0 | 0 | 0 |
TFFDDR | 1 | 1 | 0 | 0 |
IOI2:OMUX | [0, 3, 52] | [0, 3, 43] | [0, 3, 50] | [0, 3, 45] |
---|---|---|---|---|
IOI3:OMUX | [0, 3, 72] | [0, 3, 63] | [0, 3, 70] | [0, 3, 65] |
NONE | 0 | 0 | 0 | 0 |
O1 | 0 | 0 | 0 | 1 |
O2 | 0 | 0 | 1 | 0 |
OFF1 | 0 | 1 | 0 | 0 |
OFF2 | 1 | 0 | 0 | 0 |
OFFDDR | 1 | 1 | 0 | 0 |
I/O buffers — Virtex 2
Todo
document
Name | IOSTD:V2:PDRIVE | IOSTD:V2:NDRIVE | ||||||||
---|---|---|---|---|---|---|---|---|---|---|
[4] | [3] | [2] | [1] | [0] | [4] | [3] | [2] | [1] | [0] | |
AGP | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 |
BLVDS_25 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
GTL | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
GTLP | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
GTLP_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
GTL_DCI | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
HSTL_I | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
HSTL_II | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 |
HSTL_III | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
HSTL_III_18 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
HSTL_III_DCI | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
HSTL_III_DCI_18 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
HSTL_II_18 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 |
HSTL_II_DCI | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 |
HSTL_II_DCI_18 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 |
HSTL_IV | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 |
HSTL_IV_18 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 |
HSTL_IV_DCI | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 |
HSTL_IV_DCI_18 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 |
HSTL_I_18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
HSTL_I_DCI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
HSTL_I_DCI_18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
LVCMOS15.12 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
LVCMOS15.16 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
LVCMOS15.2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LVCMOS15.4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
LVCMOS15.6 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
LVCMOS15.8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
LVCMOS18.12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
LVCMOS18.16 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
LVCMOS18.2 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |
LVCMOS18.4 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
LVCMOS18.6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
LVCMOS18.8 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 |
LVCMOS25.12 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 |
LVCMOS25.16 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
LVCMOS25.2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
LVCMOS25.24 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 |
LVCMOS25.4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
LVCMOS25.6 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 |
LVCMOS25.8 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 |
LVCMOS33.12 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
LVCMOS33.16 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
LVCMOS33.2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
LVCMOS33.24 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
LVCMOS33.4 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
LVCMOS33.6 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
LVCMOS33.8 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
LVPECL_33 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
LVTTL.12 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |
LVTTL.16 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
LVTTL.2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
LVTTL.24 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
LVTTL.4 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
LVTTL.6 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |
LVTTL.8 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
OFF | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
PCI33_3 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 |
PCI66_3 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 |
PCIX | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 |
SSTL18_I | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
SSTL18_II | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
SSTL18_II_DCI | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
SSTL18_I_DCI | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
SSTL2_I | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 |
SSTL2_II | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
SSTL2_II_DCI | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
SSTL2_I_DCI | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
SSTL3_I | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |
SSTL3_II | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
SSTL3_II_DCI | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |
SSTL3_I_DCI | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
Name | IOSTD:V2:SLEW | |||
---|---|---|---|---|
[3] | [2] | [1] | [0] | |
AGP | 1 | 1 | 1 | 1 |
BLVDS_25 | 0 | 0 | 1 | 1 |
GTL | 0 | 0 | 1 | 1 |
GTLP | 0 | 0 | 1 | 1 |
GTLP_DCI | 0 | 0 | 1 | 1 |
GTL_DCI | 0 | 0 | 1 | 1 |
HSLVDCI_15 | 1 | 1 | 1 | 1 |
HSLVDCI_18 | 1 | 1 | 1 | 1 |
HSLVDCI_25 | 1 | 1 | 1 | 1 |
HSLVDCI_33 | 1 | 1 | 1 | 1 |
HSTL_I | 0 | 1 | 1 | 1 |
HSTL_II | 0 | 1 | 0 | 0 |
HSTL_III | 0 | 1 | 1 | 1 |
HSTL_III_18 | 0 | 1 | 1 | 1 |
HSTL_III_DCI | 0 | 1 | 1 | 1 |
HSTL_III_DCI_18 | 0 | 1 | 1 | 1 |
HSTL_II_18 | 0 | 1 | 1 | 1 |
HSTL_II_DCI | 0 | 1 | 0 | 0 |
HSTL_II_DCI_18 | 0 | 1 | 1 | 1 |
HSTL_IV | 0 | 1 | 1 | 1 |
HSTL_IV_18 | 0 | 1 | 1 | 1 |
HSTL_IV_DCI | 0 | 1 | 1 | 1 |
HSTL_IV_DCI_18 | 0 | 1 | 1 | 1 |
HSTL_I_18 | 0 | 1 | 1 | 1 |
HSTL_I_DCI | 0 | 1 | 1 | 1 |
HSTL_I_DCI_18 | 0 | 1 | 1 | 1 |
LVCMOS15.FAST | 1 | 1 | 1 | 1 |
LVCMOS15.SLOW | 0 | 0 | 0 | 0 |
LVCMOS18.FAST | 1 | 1 | 1 | 1 |
LVCMOS18.SLOW | 0 | 0 | 0 | 0 |
LVCMOS25.FAST | 1 | 1 | 1 | 1 |
LVCMOS25.SLOW | 0 | 0 | 0 | 0 |
LVCMOS33.FAST | 1 | 1 | 1 | 1 |
LVCMOS33.SLOW | 0 | 0 | 0 | 0 |
LVDCI_15 | 1 | 1 | 1 | 1 |
LVDCI_18 | 1 | 1 | 1 | 1 |
LVDCI_25 | 1 | 1 | 1 | 1 |
LVDCI_33 | 1 | 1 | 1 | 1 |
LVDCI_DV2_15 | 1 | 1 | 1 | 1 |
LVDCI_DV2_18 | 1 | 1 | 1 | 1 |
LVDCI_DV2_25 | 1 | 1 | 1 | 1 |
LVDCI_DV2_33 | 1 | 1 | 1 | 1 |
LVPECL_33 | 1 | 1 | 1 | 1 |
LVTTL.FAST | 1 | 1 | 1 | 1 |
LVTTL.SLOW | 0 | 0 | 0 | 0 |
PCI33_3 | 0 | 0 | 0 | 0 |
PCI66_3 | 0 | 0 | 1 | 1 |
PCIX | 0 | 0 | 1 | 1 |
SSTL18_I | 0 | 1 | 1 | 1 |
SSTL18_II | 0 | 1 | 1 | 1 |
SSTL18_II_DCI | 0 | 1 | 1 | 1 |
SSTL18_I_DCI | 0 | 1 | 1 | 1 |
SSTL2_I | 1 | 1 | 1 | 1 |
SSTL2_II | 0 | 1 | 1 | 1 |
SSTL2_II_DCI | 0 | 1 | 1 | 1 |
SSTL2_I_DCI | 1 | 1 | 1 | 1 |
SSTL3_I | 1 | 1 | 1 | 1 |
SSTL3_II | 1 | 1 | 1 | 1 |
SSTL3_II_DCI | 1 | 1 | 1 | 1 |
SSTL3_I_DCI | 1 | 1 | 1 | 1 |
VR | 1 | 1 | 1 | 1 |
Name | IOSTD:V2:OUTPUT_MISC |
---|---|
[0] | |
AGP | 0 |
BLVDS_25 | 0 |
GTL | 1 |
GTLP | 1 |
GTLP_DCI | 1 |
GTL_DCI | 1 |
HSLVDCI_15 | 0 |
HSLVDCI_18 | 0 |
HSLVDCI_25 | 0 |
HSLVDCI_33 | 0 |
HSTL_I | 0 |
HSTL_II | 0 |
HSTL_III | 0 |
HSTL_III_18 | 0 |
HSTL_III_DCI | 0 |
HSTL_III_DCI_18 | 0 |
HSTL_II_18 | 0 |
HSTL_II_DCI | 0 |
HSTL_II_DCI_18 | 0 |
HSTL_IV | 0 |
HSTL_IV_18 | 0 |
HSTL_IV_DCI | 0 |
HSTL_IV_DCI_18 | 0 |
HSTL_I_18 | 0 |
HSTL_I_DCI | 0 |
HSTL_I_DCI_18 | 0 |
LVCMOS15 | 0 |
LVCMOS18 | 0 |
LVCMOS25 | 0 |
LVCMOS33 | 0 |
LVDCI_15 | 0 |
LVDCI_18 | 0 |
LVDCI_25 | 0 |
LVDCI_33 | 0 |
LVDCI_DV2_15 | 0 |
LVDCI_DV2_18 | 0 |
LVDCI_DV2_25 | 0 |
LVDCI_DV2_33 | 0 |
LVPECL_33 | 0 |
LVTTL | 0 |
PCI33_3 | 0 |
PCI66_3 | 0 |
PCIX | 0 |
SSTL18_I | 0 |
SSTL18_II | 0 |
SSTL18_II_DCI | 0 |
SSTL18_I_DCI | 0 |
SSTL2_I | 0 |
SSTL2_II | 0 |
SSTL2_II_DCI | 0 |
SSTL2_I_DCI | 0 |
SSTL3_I | 0 |
SSTL3_II | 0 |
SSTL3_II_DCI | 0 |
SSTL3_I_DCI | 0 |
Name | IOSTD:V2:OUTPUT_DIFF | |||||
---|---|---|---|---|---|---|
[5] | [4] | [3] | [2] | [1] | [0] | |
LDT_25 | 1 | 0 | 0 | 0 | 0 | 1 |
LVDSEXT_25 | 0 | 1 | 1 | 0 | 0 | 1 |
LVDSEXT_25_DCI | 0 | 1 | 1 | 0 | 0 | 1 |
LVDSEXT_33 | 0 | 1 | 1 | 1 | 1 | 1 |
LVDSEXT_33_DCI | 0 | 1 | 1 | 1 | 1 | 1 |
LVDS_25 | 0 | 0 | 0 | 0 | 0 | 1 |
LVDS_25_DCI | 0 | 0 | 0 | 0 | 0 | 1 |
LVDS_33 | 0 | 0 | 0 | 1 | 1 | 1 |
LVDS_33_DCI | 0 | 0 | 0 | 1 | 1 | 1 |
OFF | 0 | 0 | 0 | 0 | 0 | 0 |
ULVDS_25 | 1 | 0 | 0 | 0 | 0 | 1 |
IOBS.V2.T.L2
IOB0:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
---|---|---|---|---|---|
IOB0:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] | [0, 16, 8] |
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] | [0, 8, 7] |
IOB2:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
IOB2:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] | [0, 0, 7] |
IOB3:NDRIVE | [1, 19, 11] | [1, 19, 10] | [1, 19, 6] | [1, 16, 7] | [1, 16, 10] |
IOB3:PDRIVE | [1, 19, 9] | [1, 19, 7] | [1, 19, 8] | [1, 16, 6] | [1, 16, 8] |
IOB4:NDRIVE | [1, 11, 11] | [1, 11, 10] | [1, 11, 6] | [1, 8, 6] | [1, 8, 11] |
IOB4:PDRIVE | [1, 11, 9] | [1, 11, 7] | [1, 11, 8] | [1, 8, 8] | [1, 8, 7] |
IOB5:NDRIVE | [1, 5, 9] | [1, 5, 6] | [1, 5, 8] | [1, 0, 6] | [1, 0, 9] |
IOB5:PDRIVE | [1, 5, 11] | [1, 5, 7] | [1, 5, 10] | [1, 0, 8] | [1, 0, 7] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:DISABLE_GTS | [0, 21, 10] |
---|---|
IOB0:OUTPUT_MISC | [0, 16, 11] |
IOB0:VREF | [0, 21, 9] |
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB1:OUTPUT_MISC | [0, 8, 10] |
IOB2:DISABLE_GTS | [0, 7, 11] |
IOB2:OUTPUT_MISC | [0, 0, 10] |
IOB3:DISABLE_GTS | [1, 21, 10] |
IOB3:OUTPUT_MISC | [1, 16, 11] |
IOB4:DISABLE_GTS | [1, 13, 11] |
IOB4:OUTPUT_MISC | [1, 8, 10] |
IOB4:VR | [1, 12, 8] |
IOB5:DISABLE_GTS | [1, 7, 11] |
IOB5:OUTPUT_MISC | [1, 0, 10] |
IOB5:VR | [1, 6, 7] |
IOB5:VREF | [1, 7, 7] |
Non-inverted | [0] |
IOB0:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 17, 7] | [0, 17, 6] |
---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 3, 10] | [0, 3, 7] |
IOB3:SLEW | [1, 17, 9] | [1, 17, 10] | [1, 17, 7] | [1, 17, 6] |
IOB4:SLEW | [1, 9, 8] | [1, 9, 6] | [1, 9, 10] | [1, 9, 7] |
IOB5:SLEW | [1, 3, 8] | [1, 3, 6] | [1, 3, 10] | [1, 3, 7] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
IOB3:PULL | [1, 18, 8] | [1, 18, 9] | [1, 18, 10] |
IOB4:PULL | [1, 10, 6] | [1, 10, 9] | [1, 10, 10] |
IOB5:PULL | [1, 4, 7] | [1, 4, 8] | [1, 4, 9] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
IOB3:DCI_MODE | [1, 18, 11] | [1, 20, 7] | [1, 20, 10] | [1, 20, 11] |
IOB4:DCI_MODE | [1, 10, 11] | [1, 12, 6] | [1, 12, 7] | [1, 12, 10] |
IOB5:DCI_MODE | [1, 4, 11] | [1, 6, 6] | [1, 6, 8] | [1, 6, 10] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
---|---|---|
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB2:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB3:OUTPUT_ENABLE | [1, 21, 8] | [1, 21, 7] |
IOB4:OUTPUT_ENABLE | [1, 13, 8] | [1, 13, 6] |
IOB5:OUTPUT_ENABLE | [1, 7, 10] | [1, 7, 6] |
Non-inverted | [1] | [0] |
IOB0:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
IOB2:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
IOB3:IBUF_MODE | [1, 18, 6] | [1, 18, 7] | [1, 21, 6] |
IOB4:IBUF_MODE | [1, 10, 8] | [1, 10, 7] | [1, 13, 10] |
IOB5:IBUF_MODE | [1, 4, 10] | [1, 4, 6] | [1, 7, 8] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB1:OUTPUT_DIFF | [0, 17, 8] | [0, 21, 11] | [0, 12, 9] | [0, 20, 6] | [0, 12, 11] | [0, 9, 11] |
---|---|---|---|---|---|---|
IOB3:OUTPUT_DIFF | [0, 3, 9] | [1, 21, 11] | [0, 6, 9] | [1, 20, 6] | [0, 6, 11] | [1, 17, 8] |
IOB5:OUTPUT_DIFF | [1, 9, 11] | [1, 12, 9] | [1, 6, 9] | [1, 12, 11] | [1, 6, 11] | [1, 3, 9] |
Non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
IOBS.V2.T.R2
IOB0:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
---|---|---|---|---|---|
IOB0:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] | [0, 16, 8] |
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] | [0, 8, 7] |
IOB2:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
IOB2:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] | [0, 0, 7] |
IOB3:NDRIVE | [1, 19, 11] | [1, 19, 10] | [1, 19, 6] | [1, 16, 7] | [1, 16, 10] |
IOB3:PDRIVE | [1, 19, 9] | [1, 19, 7] | [1, 19, 8] | [1, 16, 6] | [1, 16, 8] |
IOB4:NDRIVE | [1, 11, 11] | [1, 11, 10] | [1, 11, 6] | [1, 8, 6] | [1, 8, 11] |
IOB4:PDRIVE | [1, 11, 9] | [1, 11, 7] | [1, 11, 8] | [1, 8, 8] | [1, 8, 7] |
IOB5:NDRIVE | [1, 5, 9] | [1, 5, 6] | [1, 5, 8] | [1, 0, 6] | [1, 0, 9] |
IOB5:PDRIVE | [1, 5, 11] | [1, 5, 7] | [1, 5, 10] | [1, 0, 8] | [1, 0, 7] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:DISABLE_GTS | [0, 21, 10] |
---|---|
IOB0:OUTPUT_MISC | [0, 16, 11] |
IOB0:VR | [0, 20, 8] |
IOB0:VREF | [0, 21, 9] |
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB1:OUTPUT_MISC | [0, 8, 10] |
IOB1:VR | [0, 12, 8] |
IOB2:DISABLE_GTS | [0, 7, 11] |
IOB2:OUTPUT_MISC | [0, 0, 10] |
IOB3:DISABLE_GTS | [1, 21, 10] |
IOB3:OUTPUT_MISC | [1, 16, 11] |
IOB4:DISABLE_GTS | [1, 13, 11] |
IOB4:OUTPUT_MISC | [1, 8, 10] |
IOB5:DISABLE_GTS | [1, 7, 11] |
IOB5:OUTPUT_MISC | [1, 0, 10] |
IOB5:VREF | [1, 7, 7] |
Non-inverted | [0] |
IOB0:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 17, 7] | [0, 17, 6] |
---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 3, 10] | [0, 3, 7] |
IOB3:SLEW | [1, 17, 9] | [1, 17, 10] | [1, 17, 7] | [1, 17, 6] |
IOB4:SLEW | [1, 9, 8] | [1, 9, 6] | [1, 9, 10] | [1, 9, 7] |
IOB5:SLEW | [1, 3, 8] | [1, 3, 6] | [1, 3, 10] | [1, 3, 7] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
IOB3:PULL | [1, 18, 8] | [1, 18, 9] | [1, 18, 10] |
IOB4:PULL | [1, 10, 6] | [1, 10, 9] | [1, 10, 10] |
IOB5:PULL | [1, 4, 7] | [1, 4, 8] | [1, 4, 9] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
IOB3:DCI_MODE | [1, 18, 11] | [1, 20, 7] | [1, 20, 10] | [1, 20, 11] |
IOB4:DCI_MODE | [1, 10, 11] | [1, 12, 6] | [1, 12, 7] | [1, 12, 10] |
IOB5:DCI_MODE | [1, 4, 11] | [1, 6, 6] | [1, 6, 8] | [1, 6, 10] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
---|---|---|
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB2:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB3:OUTPUT_ENABLE | [1, 21, 8] | [1, 21, 7] |
IOB4:OUTPUT_ENABLE | [1, 13, 8] | [1, 13, 6] |
IOB5:OUTPUT_ENABLE | [1, 7, 10] | [1, 7, 6] |
Non-inverted | [1] | [0] |
IOB0:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
IOB2:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
IOB3:IBUF_MODE | [1, 18, 6] | [1, 18, 7] | [1, 21, 6] |
IOB4:IBUF_MODE | [1, 10, 8] | [1, 10, 7] | [1, 13, 10] |
IOB5:IBUF_MODE | [1, 4, 10] | [1, 4, 6] | [1, 7, 8] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB1:OUTPUT_DIFF | [0, 17, 8] | [0, 21, 11] | [0, 12, 9] | [0, 20, 6] | [0, 12, 11] | [0, 9, 11] |
---|---|---|---|---|---|---|
IOB3:OUTPUT_DIFF | [0, 3, 9] | [1, 21, 11] | [0, 6, 9] | [1, 20, 6] | [0, 6, 11] | [1, 17, 8] |
IOB5:OUTPUT_DIFF | [1, 9, 11] | [1, 12, 9] | [1, 6, 9] | [1, 12, 11] | [1, 6, 11] | [1, 3, 9] |
Non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
IOBS.V2.R.B2
IOB0:SLEW | [1, 3, 58] | [1, 2, 58] | [1, 3, 59] | [1, 2, 59] |
---|---|---|---|---|
IOB1:SLEW | [1, 3, 31] | [1, 2, 31] | [1, 3, 32] | [1, 2, 32] |
IOB2:SLEW | [1, 3, 4] | [1, 2, 4] | [1, 3, 5] | [1, 2, 5] |
IOB3:SLEW | [0, 3, 58] | [0, 2, 58] | [0, 3, 59] | [0, 2, 59] |
IOB4:SLEW | [0, 3, 31] | [0, 2, 31] | [0, 3, 32] | [0, 2, 32] |
IOB5:SLEW | [0, 3, 4] | [0, 2, 4] | [0, 3, 5] | [0, 2, 5] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB1:OUTPUT_DIFF | [1, 2, 60] | [1, 2, 73] | [1, 2, 46] | [1, 3, 73] | [1, 3, 46] | [1, 2, 33] |
---|---|---|---|---|---|---|
IOB3:OUTPUT_DIFF | [1, 2, 6] | [1, 2, 19] | [0, 2, 73] | [1, 3, 19] | [0, 3, 73] | [0, 2, 60] |
IOB5:OUTPUT_DIFF | [0, 2, 33] | [0, 2, 46] | [0, 2, 19] | [0, 3, 46] | [0, 3, 19] | [0, 2, 6] |
Non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
IOB0:NDRIVE | [1, 2, 66] | [1, 2, 65] | [1, 2, 64] | [1, 2, 63] | [1, 2, 62] |
---|---|---|---|---|---|
IOB0:PDRIVE | [1, 3, 66] | [1, 3, 65] | [1, 3, 64] | [1, 3, 63] | [1, 3, 62] |
IOB1:NDRIVE | [1, 2, 39] | [1, 2, 38] | [1, 2, 37] | [1, 2, 36] | [1, 2, 35] |
IOB1:PDRIVE | [1, 3, 39] | [1, 3, 38] | [1, 3, 37] | [1, 3, 36] | [1, 3, 35] |
IOB2:NDRIVE | [1, 2, 12] | [1, 2, 11] | [1, 2, 10] | [1, 2, 9] | [1, 2, 8] |
IOB2:PDRIVE | [1, 3, 12] | [1, 3, 11] | [1, 3, 10] | [1, 3, 9] | [1, 3, 8] |
IOB3:NDRIVE | [0, 2, 66] | [0, 2, 65] | [0, 2, 64] | [0, 2, 63] | [0, 2, 62] |
IOB3:PDRIVE | [0, 3, 66] | [0, 3, 65] | [0, 3, 64] | [0, 3, 63] | [0, 3, 62] |
IOB4:NDRIVE | [0, 2, 39] | [0, 2, 38] | [0, 2, 37] | [0, 2, 36] | [0, 2, 35] |
IOB4:PDRIVE | [0, 3, 39] | [0, 3, 38] | [0, 3, 37] | [0, 3, 36] | [0, 3, 35] |
IOB5:NDRIVE | [0, 2, 12] | [0, 2, 11] | [0, 2, 10] | [0, 2, 9] | [0, 2, 8] |
IOB5:PDRIVE | [0, 3, 12] | [0, 3, 11] | [0, 3, 10] | [0, 3, 9] | [0, 3, 8] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:IBUF_MODE | [1, 3, 69] | [1, 2, 69] | [1, 2, 70] |
---|---|---|---|
IOB1:IBUF_MODE | [1, 3, 42] | [1, 2, 42] | [1, 2, 43] |
IOB2:IBUF_MODE | [1, 3, 15] | [1, 2, 15] | [1, 2, 16] |
IOB3:IBUF_MODE | [0, 3, 69] | [0, 2, 69] | [0, 2, 70] |
IOB4:IBUF_MODE | [0, 3, 42] | [0, 2, 42] | [0, 2, 43] |
IOB5:IBUF_MODE | [0, 3, 15] | [0, 2, 15] | [0, 2, 16] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:OUTPUT_ENABLE | [1, 3, 70] | [1, 2, 71] |
---|---|---|
IOB1:OUTPUT_ENABLE | [1, 3, 43] | [1, 2, 44] |
IOB2:OUTPUT_ENABLE | [1, 3, 16] | [1, 2, 17] |
IOB3:OUTPUT_ENABLE | [0, 3, 70] | [0, 2, 71] |
IOB4:OUTPUT_ENABLE | [0, 3, 43] | [0, 2, 44] |
IOB5:OUTPUT_ENABLE | [0, 3, 16] | [0, 2, 17] |
Non-inverted | [1] | [0] |
IOB0:DISABLE_GTS | [1, 2, 72] |
---|---|
IOB0:OUTPUT_MISC | [1, 3, 61] |
IOB0:VREF | [1, 3, 71] |
IOB1:DISABLE_GTS | [1, 2, 45] |
IOB1:OUTPUT_MISC | [1, 3, 34] |
IOB2:DISABLE_GTS | [1, 2, 18] |
IOB2:OUTPUT_MISC | [1, 3, 7] |
IOB2:VR | [1, 3, 21] |
IOB3:DISABLE_GTS | [0, 2, 72] |
IOB3:OUTPUT_MISC | [0, 3, 61] |
IOB3:VR | [0, 3, 75] |
IOB4:DISABLE_GTS | [0, 2, 45] |
IOB4:OUTPUT_MISC | [0, 3, 34] |
IOB5:DISABLE_GTS | [0, 2, 18] |
IOB5:OUTPUT_MISC | [0, 3, 7] |
Non-inverted | [0] |
IOB0:DCI_MODE | [1, 2, 67] | [1, 2, 75] | [1, 3, 74] | [1, 2, 74] |
---|---|---|---|---|
IOB1:DCI_MODE | [1, 2, 40] | [1, 2, 48] | [1, 3, 47] | [1, 2, 47] |
IOB2:DCI_MODE | [1, 2, 13] | [1, 2, 21] | [1, 3, 20] | [1, 2, 20] |
IOB3:DCI_MODE | [0, 2, 67] | [0, 2, 75] | [0, 3, 74] | [0, 2, 74] |
IOB4:DCI_MODE | [0, 2, 40] | [0, 2, 48] | [0, 3, 47] | [0, 2, 47] |
IOB5:DCI_MODE | [0, 2, 13] | [0, 2, 21] | [0, 3, 20] | [0, 2, 20] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:PULL | [1, 3, 68] | [1, 2, 68] | [1, 3, 67] |
---|---|---|---|
IOB1:PULL | [1, 3, 41] | [1, 2, 41] | [1, 3, 40] |
IOB2:PULL | [1, 3, 14] | [1, 2, 14] | [1, 3, 13] |
IOB3:PULL | [0, 3, 68] | [0, 2, 68] | [0, 3, 67] |
IOB4:PULL | [0, 3, 41] | [0, 2, 41] | [0, 3, 40] |
IOB5:PULL | [0, 3, 14] | [0, 2, 14] | [0, 3, 13] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOBS.V2.R.T2
IOB0:SLEW | [1, 3, 58] | [1, 2, 58] | [1, 3, 59] | [1, 2, 59] |
---|---|---|---|---|
IOB1:SLEW | [1, 3, 31] | [1, 2, 31] | [1, 3, 32] | [1, 2, 32] |
IOB2:SLEW | [1, 3, 4] | [1, 2, 4] | [1, 3, 5] | [1, 2, 5] |
IOB3:SLEW | [0, 3, 58] | [0, 2, 58] | [0, 3, 59] | [0, 2, 59] |
IOB4:SLEW | [0, 3, 31] | [0, 2, 31] | [0, 3, 32] | [0, 2, 32] |
IOB5:SLEW | [0, 3, 4] | [0, 2, 4] | [0, 3, 5] | [0, 2, 5] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB1:OUTPUT_DIFF | [1, 2, 60] | [1, 2, 73] | [1, 2, 46] | [1, 3, 73] | [1, 3, 46] | [1, 2, 33] |
---|---|---|---|---|---|---|
IOB3:OUTPUT_DIFF | [1, 2, 6] | [1, 2, 19] | [0, 2, 73] | [1, 3, 19] | [0, 3, 73] | [0, 2, 60] |
IOB5:OUTPUT_DIFF | [0, 2, 33] | [0, 2, 46] | [0, 2, 19] | [0, 3, 46] | [0, 3, 19] | [0, 2, 6] |
Non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
IOB0:NDRIVE | [1, 2, 66] | [1, 2, 65] | [1, 2, 64] | [1, 2, 63] | [1, 2, 62] |
---|---|---|---|---|---|
IOB0:PDRIVE | [1, 3, 66] | [1, 3, 65] | [1, 3, 64] | [1, 3, 63] | [1, 3, 62] |
IOB1:NDRIVE | [1, 2, 39] | [1, 2, 38] | [1, 2, 37] | [1, 2, 36] | [1, 2, 35] |
IOB1:PDRIVE | [1, 3, 39] | [1, 3, 38] | [1, 3, 37] | [1, 3, 36] | [1, 3, 35] |
IOB2:NDRIVE | [1, 2, 12] | [1, 2, 11] | [1, 2, 10] | [1, 2, 9] | [1, 2, 8] |
IOB2:PDRIVE | [1, 3, 12] | [1, 3, 11] | [1, 3, 10] | [1, 3, 9] | [1, 3, 8] |
IOB3:NDRIVE | [0, 2, 66] | [0, 2, 65] | [0, 2, 64] | [0, 2, 63] | [0, 2, 62] |
IOB3:PDRIVE | [0, 3, 66] | [0, 3, 65] | [0, 3, 64] | [0, 3, 63] | [0, 3, 62] |
IOB4:NDRIVE | [0, 2, 39] | [0, 2, 38] | [0, 2, 37] | [0, 2, 36] | [0, 2, 35] |
IOB4:PDRIVE | [0, 3, 39] | [0, 3, 38] | [0, 3, 37] | [0, 3, 36] | [0, 3, 35] |
IOB5:NDRIVE | [0, 2, 12] | [0, 2, 11] | [0, 2, 10] | [0, 2, 9] | [0, 2, 8] |
IOB5:PDRIVE | [0, 3, 12] | [0, 3, 11] | [0, 3, 10] | [0, 3, 9] | [0, 3, 8] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:IBUF_MODE | [1, 3, 69] | [1, 2, 69] | [1, 2, 70] |
---|---|---|---|
IOB1:IBUF_MODE | [1, 3, 42] | [1, 2, 42] | [1, 2, 43] |
IOB2:IBUF_MODE | [1, 3, 15] | [1, 2, 15] | [1, 2, 16] |
IOB3:IBUF_MODE | [0, 3, 69] | [0, 2, 69] | [0, 2, 70] |
IOB4:IBUF_MODE | [0, 3, 42] | [0, 2, 42] | [0, 2, 43] |
IOB5:IBUF_MODE | [0, 3, 15] | [0, 2, 15] | [0, 2, 16] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:OUTPUT_ENABLE | [1, 3, 70] | [1, 2, 71] |
---|---|---|
IOB1:OUTPUT_ENABLE | [1, 3, 43] | [1, 2, 44] |
IOB2:OUTPUT_ENABLE | [1, 3, 16] | [1, 2, 17] |
IOB3:OUTPUT_ENABLE | [0, 3, 70] | [0, 2, 71] |
IOB4:OUTPUT_ENABLE | [0, 3, 43] | [0, 2, 44] |
IOB5:OUTPUT_ENABLE | [0, 3, 16] | [0, 2, 17] |
Non-inverted | [1] | [0] |
IOB0:DISABLE_GTS | [1, 2, 72] |
---|---|
IOB0:OUTPUT_MISC | [1, 3, 61] |
IOB1:DISABLE_GTS | [1, 2, 45] |
IOB1:OUTPUT_MISC | [1, 3, 34] |
IOB2:DISABLE_GTS | [1, 2, 18] |
IOB2:OUTPUT_MISC | [1, 3, 7] |
IOB2:VR | [1, 3, 21] |
IOB3:DISABLE_GTS | [0, 2, 72] |
IOB3:OUTPUT_MISC | [0, 3, 61] |
IOB3:VR | [0, 3, 75] |
IOB4:DISABLE_GTS | [0, 2, 45] |
IOB4:OUTPUT_MISC | [0, 3, 34] |
IOB5:DISABLE_GTS | [0, 2, 18] |
IOB5:OUTPUT_MISC | [0, 3, 7] |
IOB5:VREF | [0, 3, 17] |
Non-inverted | [0] |
IOB0:DCI_MODE | [1, 2, 67] | [1, 2, 75] | [1, 3, 74] | [1, 2, 74] |
---|---|---|---|---|
IOB1:DCI_MODE | [1, 2, 40] | [1, 2, 48] | [1, 3, 47] | [1, 2, 47] |
IOB2:DCI_MODE | [1, 2, 13] | [1, 2, 21] | [1, 3, 20] | [1, 2, 20] |
IOB3:DCI_MODE | [0, 2, 67] | [0, 2, 75] | [0, 3, 74] | [0, 2, 74] |
IOB4:DCI_MODE | [0, 2, 40] | [0, 2, 48] | [0, 3, 47] | [0, 2, 47] |
IOB5:DCI_MODE | [0, 2, 13] | [0, 2, 21] | [0, 3, 20] | [0, 2, 20] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:PULL | [1, 3, 68] | [1, 2, 68] | [1, 3, 67] |
---|---|---|---|
IOB1:PULL | [1, 3, 41] | [1, 2, 41] | [1, 3, 40] |
IOB2:PULL | [1, 3, 14] | [1, 2, 14] | [1, 3, 13] |
IOB3:PULL | [0, 3, 68] | [0, 2, 68] | [0, 3, 67] |
IOB4:PULL | [0, 3, 41] | [0, 2, 41] | [0, 3, 40] |
IOB5:PULL | [0, 3, 14] | [0, 2, 14] | [0, 3, 13] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOBS.V2.B.L2
IOB0:NDRIVE | [1, 5, 9] | [1, 5, 6] | [1, 5, 8] | [1, 0, 6] | [1, 0, 9] |
---|---|---|---|---|---|
IOB0:PDRIVE | [1, 5, 11] | [1, 5, 7] | [1, 5, 10] | [1, 0, 8] | [1, 0, 7] |
IOB1:NDRIVE | [1, 11, 11] | [1, 11, 10] | [1, 11, 6] | [1, 8, 6] | [1, 8, 11] |
IOB1:PDRIVE | [1, 11, 9] | [1, 11, 7] | [1, 11, 8] | [1, 8, 8] | [1, 8, 7] |
IOB2:NDRIVE | [1, 19, 11] | [1, 19, 10] | [1, 19, 6] | [1, 16, 7] | [1, 16, 10] |
IOB2:PDRIVE | [1, 19, 9] | [1, 19, 7] | [1, 19, 8] | [1, 16, 6] | [1, 16, 8] |
IOB3:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
IOB3:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] | [0, 0, 7] |
IOB4:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB4:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] | [0, 8, 7] |
IOB5:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
IOB5:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] | [0, 16, 8] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:DISABLE_GTS | [1, 7, 11] |
---|---|
IOB0:OUTPUT_MISC | [1, 0, 10] |
IOB0:VR | [1, 6, 7] |
IOB0:VREF | [1, 7, 7] |
IOB1:DISABLE_GTS | [1, 13, 11] |
IOB1:OUTPUT_MISC | [1, 8, 10] |
IOB1:VR | [1, 12, 8] |
IOB2:DISABLE_GTS | [1, 21, 10] |
IOB2:OUTPUT_MISC | [1, 16, 11] |
IOB3:DISABLE_GTS | [0, 7, 11] |
IOB3:OUTPUT_MISC | [0, 0, 10] |
IOB4:DISABLE_GTS | [0, 13, 11] |
IOB4:OUTPUT_MISC | [0, 8, 10] |
IOB5:DISABLE_GTS | [0, 21, 10] |
IOB5:OUTPUT_MISC | [0, 16, 11] |
IOB5:VREF | [0, 21, 9] |
Non-inverted | [0] |
IOB0:SLEW | [1, 3, 8] | [1, 3, 6] | [1, 3, 10] | [1, 3, 7] |
---|---|---|---|---|
IOB1:SLEW | [1, 9, 8] | [1, 9, 6] | [1, 9, 10] | [1, 9, 7] |
IOB2:SLEW | [1, 17, 9] | [1, 17, 10] | [1, 17, 7] | [1, 17, 6] |
IOB3:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 3, 10] | [0, 3, 7] |
IOB4:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 9, 10] | [0, 9, 7] |
IOB5:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 17, 7] | [0, 17, 6] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB1:OUTPUT_DIFF | [1, 3, 9] | [1, 12, 9] | [1, 6, 9] | [1, 12, 11] | [1, 6, 11] | [1, 9, 11] |
---|---|---|---|---|---|---|
IOB3:OUTPUT_DIFF | [1, 17, 8] | [1, 21, 11] | [0, 6, 9] | [1, 20, 6] | [0, 6, 11] | [0, 3, 9] |
IOB5:OUTPUT_DIFF | [0, 9, 11] | [0, 21, 11] | [0, 12, 9] | [0, 20, 6] | [0, 12, 11] | [0, 17, 8] |
Non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
IOB0:PULL | [1, 4, 7] | [1, 4, 8] | [1, 4, 9] |
---|---|---|---|
IOB1:PULL | [1, 10, 6] | [1, 10, 9] | [1, 10, 10] |
IOB2:PULL | [1, 18, 8] | [1, 18, 9] | [1, 18, 10] |
IOB3:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
IOB4:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB5:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [1, 4, 11] | [1, 6, 6] | [1, 6, 8] | [1, 6, 10] |
---|---|---|---|---|
IOB1:DCI_MODE | [1, 10, 11] | [1, 12, 6] | [1, 12, 7] | [1, 12, 10] |
IOB2:DCI_MODE | [1, 18, 11] | [1, 20, 7] | [1, 20, 10] | [1, 20, 11] |
IOB3:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
IOB4:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB5:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:OUTPUT_ENABLE | [1, 7, 10] | [1, 7, 6] |
---|---|---|
IOB1:OUTPUT_ENABLE | [1, 13, 8] | [1, 13, 6] |
IOB2:OUTPUT_ENABLE | [1, 21, 8] | [1, 21, 7] |
IOB3:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB4:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB5:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
Non-inverted | [1] | [0] |
IOB0:IBUF_MODE | [1, 4, 10] | [1, 4, 6] | [1, 7, 8] |
---|---|---|---|
IOB1:IBUF_MODE | [1, 10, 8] | [1, 10, 7] | [1, 13, 10] |
IOB2:IBUF_MODE | [1, 18, 6] | [1, 18, 7] | [1, 21, 6] |
IOB3:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
IOB4:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
IOB5:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOBS.V2.B.R2
IOB0:NDRIVE | [1, 5, 9] | [1, 5, 6] | [1, 5, 8] | [1, 0, 6] | [1, 0, 9] |
---|---|---|---|---|---|
IOB0:PDRIVE | [1, 5, 11] | [1, 5, 7] | [1, 5, 10] | [1, 0, 8] | [1, 0, 7] |
IOB1:NDRIVE | [1, 11, 11] | [1, 11, 10] | [1, 11, 6] | [1, 8, 6] | [1, 8, 11] |
IOB1:PDRIVE | [1, 11, 9] | [1, 11, 7] | [1, 11, 8] | [1, 8, 8] | [1, 8, 7] |
IOB2:NDRIVE | [1, 19, 11] | [1, 19, 10] | [1, 19, 6] | [1, 16, 7] | [1, 16, 10] |
IOB2:PDRIVE | [1, 19, 9] | [1, 19, 7] | [1, 19, 8] | [1, 16, 6] | [1, 16, 8] |
IOB3:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
IOB3:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] | [0, 0, 7] |
IOB4:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB4:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] | [0, 8, 7] |
IOB5:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
IOB5:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] | [0, 16, 8] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:DISABLE_GTS | [1, 7, 11] |
---|---|
IOB0:OUTPUT_MISC | [1, 0, 10] |
IOB0:VREF | [1, 7, 7] |
IOB1:DISABLE_GTS | [1, 13, 11] |
IOB1:OUTPUT_MISC | [1, 8, 10] |
IOB2:DISABLE_GTS | [1, 21, 10] |
IOB2:OUTPUT_MISC | [1, 16, 11] |
IOB3:DISABLE_GTS | [0, 7, 11] |
IOB3:OUTPUT_MISC | [0, 0, 10] |
IOB4:DISABLE_GTS | [0, 13, 11] |
IOB4:OUTPUT_MISC | [0, 8, 10] |
IOB4:VR | [0, 12, 8] |
IOB5:DISABLE_GTS | [0, 21, 10] |
IOB5:OUTPUT_MISC | [0, 16, 11] |
IOB5:VR | [0, 20, 8] |
IOB5:VREF | [0, 21, 9] |
Non-inverted | [0] |
IOB0:SLEW | [1, 3, 8] | [1, 3, 6] | [1, 3, 10] | [1, 3, 7] |
---|---|---|---|---|
IOB1:SLEW | [1, 9, 8] | [1, 9, 6] | [1, 9, 10] | [1, 9, 7] |
IOB2:SLEW | [1, 17, 9] | [1, 17, 10] | [1, 17, 7] | [1, 17, 6] |
IOB3:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 3, 10] | [0, 3, 7] |
IOB4:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 9, 10] | [0, 9, 7] |
IOB5:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 17, 7] | [0, 17, 6] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB1:OUTPUT_DIFF | [1, 3, 9] | [1, 12, 9] | [1, 6, 9] | [1, 12, 11] | [1, 6, 11] | [1, 9, 11] |
---|---|---|---|---|---|---|
IOB3:OUTPUT_DIFF | [1, 17, 8] | [1, 21, 11] | [0, 6, 9] | [1, 20, 6] | [0, 6, 11] | [0, 3, 9] |
IOB5:OUTPUT_DIFF | [0, 9, 11] | [0, 21, 11] | [0, 12, 9] | [0, 20, 6] | [0, 12, 11] | [0, 17, 8] |
Non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
IOB0:PULL | [1, 4, 7] | [1, 4, 8] | [1, 4, 9] |
---|---|---|---|
IOB1:PULL | [1, 10, 6] | [1, 10, 9] | [1, 10, 10] |
IOB2:PULL | [1, 18, 8] | [1, 18, 9] | [1, 18, 10] |
IOB3:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
IOB4:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB5:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [1, 4, 11] | [1, 6, 6] | [1, 6, 8] | [1, 6, 10] |
---|---|---|---|---|
IOB1:DCI_MODE | [1, 10, 11] | [1, 12, 6] | [1, 12, 7] | [1, 12, 10] |
IOB2:DCI_MODE | [1, 18, 11] | [1, 20, 7] | [1, 20, 10] | [1, 20, 11] |
IOB3:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
IOB4:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB5:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:OUTPUT_ENABLE | [1, 7, 10] | [1, 7, 6] |
---|---|---|
IOB1:OUTPUT_ENABLE | [1, 13, 8] | [1, 13, 6] |
IOB2:OUTPUT_ENABLE | [1, 21, 8] | [1, 21, 7] |
IOB3:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB4:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB5:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
Non-inverted | [1] | [0] |
IOB0:IBUF_MODE | [1, 4, 10] | [1, 4, 6] | [1, 7, 8] |
---|---|---|---|
IOB1:IBUF_MODE | [1, 10, 8] | [1, 10, 7] | [1, 13, 10] |
IOB2:IBUF_MODE | [1, 18, 6] | [1, 18, 7] | [1, 21, 6] |
IOB3:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
IOB4:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
IOB5:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOBS.V2.L.B2
IOB0:SLEW | [0, 3, 4] | [0, 2, 4] | [0, 3, 5] | [0, 2, 5] |
---|---|---|---|---|
IOB1:SLEW | [0, 3, 31] | [0, 2, 31] | [0, 3, 32] | [0, 2, 32] |
IOB2:SLEW | [0, 3, 58] | [0, 2, 58] | [0, 3, 59] | [0, 2, 59] |
IOB3:SLEW | [1, 3, 4] | [1, 2, 4] | [1, 3, 5] | [1, 2, 5] |
IOB4:SLEW | [1, 3, 31] | [1, 2, 31] | [1, 3, 32] | [1, 2, 32] |
IOB5:SLEW | [1, 3, 58] | [1, 2, 58] | [1, 3, 59] | [1, 2, 59] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:OUTPUT_DIFF | [0, 2, 33] | [0, 2, 46] | [0, 2, 19] | [0, 3, 46] | [0, 3, 19] | [0, 2, 6] |
---|---|---|---|---|---|---|
IOB2:OUTPUT_DIFF | [1, 2, 6] | [1, 2, 19] | [0, 2, 73] | [1, 3, 19] | [0, 3, 73] | [0, 2, 60] |
IOB4:OUTPUT_DIFF | [1, 2, 60] | [1, 2, 73] | [1, 2, 46] | [1, 3, 73] | [1, 3, 46] | [1, 2, 33] |
Non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
IOB0:NDRIVE | [0, 2, 12] | [0, 2, 11] | [0, 2, 10] | [0, 2, 9] | [0, 2, 8] |
---|---|---|---|---|---|
IOB0:PDRIVE | [0, 3, 12] | [0, 3, 11] | [0, 3, 10] | [0, 3, 9] | [0, 3, 8] |
IOB1:NDRIVE | [0, 2, 39] | [0, 2, 38] | [0, 2, 37] | [0, 2, 36] | [0, 2, 35] |
IOB1:PDRIVE | [0, 3, 39] | [0, 3, 38] | [0, 3, 37] | [0, 3, 36] | [0, 3, 35] |
IOB2:NDRIVE | [0, 2, 66] | [0, 2, 65] | [0, 2, 64] | [0, 2, 63] | [0, 2, 62] |
IOB2:PDRIVE | [0, 3, 66] | [0, 3, 65] | [0, 3, 64] | [0, 3, 63] | [0, 3, 62] |
IOB3:NDRIVE | [1, 2, 12] | [1, 2, 11] | [1, 2, 10] | [1, 2, 9] | [1, 2, 8] |
IOB3:PDRIVE | [1, 3, 12] | [1, 3, 11] | [1, 3, 10] | [1, 3, 9] | [1, 3, 8] |
IOB4:NDRIVE | [1, 2, 39] | [1, 2, 38] | [1, 2, 37] | [1, 2, 36] | [1, 2, 35] |
IOB4:PDRIVE | [1, 3, 39] | [1, 3, 38] | [1, 3, 37] | [1, 3, 36] | [1, 3, 35] |
IOB5:NDRIVE | [1, 2, 66] | [1, 2, 65] | [1, 2, 64] | [1, 2, 63] | [1, 2, 62] |
IOB5:PDRIVE | [1, 3, 66] | [1, 3, 65] | [1, 3, 64] | [1, 3, 63] | [1, 3, 62] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:IBUF_MODE | [0, 3, 15] | [0, 2, 15] | [0, 2, 16] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 3, 42] | [0, 2, 42] | [0, 2, 43] |
IOB2:IBUF_MODE | [0, 3, 69] | [0, 2, 69] | [0, 2, 70] |
IOB3:IBUF_MODE | [1, 3, 15] | [1, 2, 15] | [1, 2, 16] |
IOB4:IBUF_MODE | [1, 3, 42] | [1, 2, 42] | [1, 2, 43] |
IOB5:IBUF_MODE | [1, 3, 69] | [1, 2, 69] | [1, 2, 70] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:OUTPUT_ENABLE | [0, 3, 16] | [0, 2, 17] |
---|---|---|
IOB1:OUTPUT_ENABLE | [0, 3, 43] | [0, 2, 44] |
IOB2:OUTPUT_ENABLE | [0, 3, 70] | [0, 2, 71] |
IOB3:OUTPUT_ENABLE | [1, 3, 16] | [1, 2, 17] |
IOB4:OUTPUT_ENABLE | [1, 3, 43] | [1, 2, 44] |
IOB5:OUTPUT_ENABLE | [1, 3, 70] | [1, 2, 71] |
Non-inverted | [1] | [0] |
IOB0:DISABLE_GTS | [0, 2, 18] |
---|---|
IOB0:OUTPUT_MISC | [0, 3, 7] |
IOB1:DISABLE_GTS | [0, 2, 45] |
IOB1:OUTPUT_MISC | [0, 3, 34] |
IOB2:DISABLE_GTS | [0, 2, 72] |
IOB2:OUTPUT_MISC | [0, 3, 61] |
IOB2:VR | [0, 3, 75] |
IOB3:DISABLE_GTS | [1, 2, 18] |
IOB3:OUTPUT_MISC | [1, 3, 7] |
IOB3:VR | [1, 3, 21] |
IOB4:DISABLE_GTS | [1, 2, 45] |
IOB4:OUTPUT_MISC | [1, 3, 34] |
IOB5:DISABLE_GTS | [1, 2, 72] |
IOB5:OUTPUT_MISC | [1, 3, 61] |
IOB5:VREF | [1, 3, 71] |
Non-inverted | [0] |
IOB0:DCI_MODE | [0, 2, 13] | [0, 2, 21] | [0, 3, 20] | [0, 2, 20] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 2, 40] | [0, 2, 48] | [0, 3, 47] | [0, 2, 47] |
IOB2:DCI_MODE | [0, 2, 67] | [0, 2, 75] | [0, 3, 74] | [0, 2, 74] |
IOB3:DCI_MODE | [1, 2, 13] | [1, 2, 21] | [1, 3, 20] | [1, 2, 20] |
IOB4:DCI_MODE | [1, 2, 40] | [1, 2, 48] | [1, 3, 47] | [1, 2, 47] |
IOB5:DCI_MODE | [1, 2, 67] | [1, 2, 75] | [1, 3, 74] | [1, 2, 74] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:PULL | [0, 3, 14] | [0, 2, 14] | [0, 3, 13] |
---|---|---|---|
IOB1:PULL | [0, 3, 41] | [0, 2, 41] | [0, 3, 40] |
IOB2:PULL | [0, 3, 68] | [0, 2, 68] | [0, 3, 67] |
IOB3:PULL | [1, 3, 14] | [1, 2, 14] | [1, 3, 13] |
IOB4:PULL | [1, 3, 41] | [1, 2, 41] | [1, 3, 40] |
IOB5:PULL | [1, 3, 68] | [1, 2, 68] | [1, 3, 67] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOBS.V2.L.T2
IOB0:SLEW | [0, 3, 4] | [0, 2, 4] | [0, 3, 5] | [0, 2, 5] |
---|---|---|---|---|
IOB1:SLEW | [0, 3, 31] | [0, 2, 31] | [0, 3, 32] | [0, 2, 32] |
IOB2:SLEW | [0, 3, 58] | [0, 2, 58] | [0, 3, 59] | [0, 2, 59] |
IOB3:SLEW | [1, 3, 4] | [1, 2, 4] | [1, 3, 5] | [1, 2, 5] |
IOB4:SLEW | [1, 3, 31] | [1, 2, 31] | [1, 3, 32] | [1, 2, 32] |
IOB5:SLEW | [1, 3, 58] | [1, 2, 58] | [1, 3, 59] | [1, 2, 59] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:OUTPUT_DIFF | [0, 2, 33] | [0, 2, 46] | [0, 2, 19] | [0, 3, 46] | [0, 3, 19] | [0, 2, 6] |
---|---|---|---|---|---|---|
IOB2:OUTPUT_DIFF | [1, 2, 6] | [1, 2, 19] | [0, 2, 73] | [1, 3, 19] | [0, 3, 73] | [0, 2, 60] |
IOB4:OUTPUT_DIFF | [1, 2, 60] | [1, 2, 73] | [1, 2, 46] | [1, 3, 73] | [1, 3, 46] | [1, 2, 33] |
Non-inverted | [5] | [4] | [3] | [2] | [1] | [0] |
IOB0:NDRIVE | [0, 2, 12] | [0, 2, 11] | [0, 2, 10] | [0, 2, 9] | [0, 2, 8] |
---|---|---|---|---|---|
IOB0:PDRIVE | [0, 3, 12] | [0, 3, 11] | [0, 3, 10] | [0, 3, 9] | [0, 3, 8] |
IOB1:NDRIVE | [0, 2, 39] | [0, 2, 38] | [0, 2, 37] | [0, 2, 36] | [0, 2, 35] |
IOB1:PDRIVE | [0, 3, 39] | [0, 3, 38] | [0, 3, 37] | [0, 3, 36] | [0, 3, 35] |
IOB2:NDRIVE | [0, 2, 66] | [0, 2, 65] | [0, 2, 64] | [0, 2, 63] | [0, 2, 62] |
IOB2:PDRIVE | [0, 3, 66] | [0, 3, 65] | [0, 3, 64] | [0, 3, 63] | [0, 3, 62] |
IOB3:NDRIVE | [1, 2, 12] | [1, 2, 11] | [1, 2, 10] | [1, 2, 9] | [1, 2, 8] |
IOB3:PDRIVE | [1, 3, 12] | [1, 3, 11] | [1, 3, 10] | [1, 3, 9] | [1, 3, 8] |
IOB4:NDRIVE | [1, 2, 39] | [1, 2, 38] | [1, 2, 37] | [1, 2, 36] | [1, 2, 35] |
IOB4:PDRIVE | [1, 3, 39] | [1, 3, 38] | [1, 3, 37] | [1, 3, 36] | [1, 3, 35] |
IOB5:NDRIVE | [1, 2, 66] | [1, 2, 65] | [1, 2, 64] | [1, 2, 63] | [1, 2, 62] |
IOB5:PDRIVE | [1, 3, 66] | [1, 3, 65] | [1, 3, 64] | [1, 3, 63] | [1, 3, 62] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:IBUF_MODE | [0, 3, 15] | [0, 2, 15] | [0, 2, 16] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 3, 42] | [0, 2, 42] | [0, 2, 43] |
IOB2:IBUF_MODE | [0, 3, 69] | [0, 2, 69] | [0, 2, 70] |
IOB3:IBUF_MODE | [1, 3, 15] | [1, 2, 15] | [1, 2, 16] |
IOB4:IBUF_MODE | [1, 3, 42] | [1, 2, 42] | [1, 2, 43] |
IOB5:IBUF_MODE | [1, 3, 69] | [1, 2, 69] | [1, 2, 70] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:OUTPUT_ENABLE | [0, 3, 16] | [0, 2, 17] |
---|---|---|
IOB1:OUTPUT_ENABLE | [0, 3, 43] | [0, 2, 44] |
IOB2:OUTPUT_ENABLE | [0, 3, 70] | [0, 2, 71] |
IOB3:OUTPUT_ENABLE | [1, 3, 16] | [1, 2, 17] |
IOB4:OUTPUT_ENABLE | [1, 3, 43] | [1, 2, 44] |
IOB5:OUTPUT_ENABLE | [1, 3, 70] | [1, 2, 71] |
Non-inverted | [1] | [0] |
IOB0:DISABLE_GTS | [0, 2, 18] |
---|---|
IOB0:OUTPUT_MISC | [0, 3, 7] |
IOB0:VREF | [0, 3, 17] |
IOB1:DISABLE_GTS | [0, 2, 45] |
IOB1:OUTPUT_MISC | [0, 3, 34] |
IOB2:DISABLE_GTS | [0, 2, 72] |
IOB2:OUTPUT_MISC | [0, 3, 61] |
IOB2:VR | [0, 3, 75] |
IOB3:DISABLE_GTS | [1, 2, 18] |
IOB3:OUTPUT_MISC | [1, 3, 7] |
IOB3:VR | [1, 3, 21] |
IOB4:DISABLE_GTS | [1, 2, 45] |
IOB4:OUTPUT_MISC | [1, 3, 34] |
IOB5:DISABLE_GTS | [1, 2, 72] |
IOB5:OUTPUT_MISC | [1, 3, 61] |
Non-inverted | [0] |
IOB0:DCI_MODE | [0, 2, 13] | [0, 2, 21] | [0, 3, 20] | [0, 2, 20] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 2, 40] | [0, 2, 48] | [0, 3, 47] | [0, 2, 47] |
IOB2:DCI_MODE | [0, 2, 67] | [0, 2, 75] | [0, 3, 74] | [0, 2, 74] |
IOB3:DCI_MODE | [1, 2, 13] | [1, 2, 21] | [1, 3, 20] | [1, 2, 20] |
IOB4:DCI_MODE | [1, 2, 40] | [1, 2, 48] | [1, 3, 47] | [1, 2, 47] |
IOB5:DCI_MODE | [1, 2, 67] | [1, 2, 75] | [1, 3, 74] | [1, 2, 74] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:PULL | [0, 3, 14] | [0, 2, 14] | [0, 3, 13] |
---|---|---|---|
IOB1:PULL | [0, 3, 41] | [0, 2, 41] | [0, 3, 40] |
IOB2:PULL | [0, 3, 68] | [0, 2, 68] | [0, 3, 67] |
IOB3:PULL | [1, 3, 14] | [1, 2, 14] | [1, 3, 13] |
IOB4:PULL | [1, 3, 41] | [1, 2, 41] | [1, 3, 40] |
IOB5:PULL | [1, 3, 68] | [1, 2, 68] | [1, 3, 67] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
I/O buffers — Virtex 2 Pro
Todo
document
Name | IOSTD:V2P:PDRIVE | IOSTD:V2P:NDRIVE | |||||||
---|---|---|---|---|---|---|---|---|---|
[3] | [2] | [1] | [0] | [4] | [3] | [2] | [1] | [0] | |
BLVDS_25 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 |
GTL | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
GTLP | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
GTLP_DCI | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
GTL_DCI | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
HSTL_I | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
HSTL_II | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
HSTL_III | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
HSTL_III_18 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
HSTL_III_DCI | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
HSTL_III_DCI_18 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
HSTL_II_18 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
HSTL_II_DCI | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
HSTL_II_DCI_18 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
HSTL_IV | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
HSTL_IV_18 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
HSTL_IV_DCI | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
HSTL_IV_DCI_18 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
HSTL_I_18 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
HSTL_I_DCI | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
HSTL_I_DCI_18 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
LVCMOS15.12 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
LVCMOS15.16 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |
LVCMOS15.2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
LVCMOS15.4 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
LVCMOS15.6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
LVCMOS15.8 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
LVCMOS18.12 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |
LVCMOS18.16 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
LVCMOS18.2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
LVCMOS18.4 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
LVCMOS18.6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
LVCMOS18.8 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
LVCMOS25.12 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 |
LVCMOS25.16 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
LVCMOS25.2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
LVCMOS25.24 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
LVCMOS25.4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
LVCMOS25.6 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |
LVCMOS25.8 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
LVCMOS33.12 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
LVCMOS33.16 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
LVCMOS33.2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
LVCMOS33.24 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
LVCMOS33.4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
LVCMOS33.6 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
LVCMOS33.8 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 |
LVPECL_25 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
LVTTL.12 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 |
LVTTL.16 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
LVTTL.2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
LVTTL.24 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 |
LVTTL.4 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
LVTTL.6 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
LVTTL.8 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
OFF | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
PCI33_3 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 |
PCI66_3 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 |
PCIX | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
SSTL18_I | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
SSTL18_II | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 |
SSTL18_II_DCI | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 |
SSTL18_I_DCI | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
SSTL2_I | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |
SSTL2_II | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
SSTL2_II_DCI | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
SSTL2_I_DCI | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
Name | IOSTD:V2P:SLEW | ||||
---|---|---|---|---|---|
[4] | [3] | [2] | [1] | [0] | |
BLVDS_25 | 0 | 1 | 1 | 1 | 1 |
GTL | 0 | 0 | 0 | 1 | 1 |
GTLP | 1 | 0 | 0 | 1 | 1 |
GTLP_DCI | 1 | 1 | 1 | 0 | 0 |
GTL_DCI | 0 | 1 | 1 | 0 | 0 |
HSLVDCI_15 | 1 | 1 | 1 | 1 | 1 |
HSLVDCI_18 | 1 | 1 | 1 | 1 | 1 |
HSLVDCI_25 | 1 | 1 | 1 | 1 | 1 |
HSLVDCI_33 | 1 | 1 | 1 | 1 | 1 |
HSTL_I | 0 | 1 | 1 | 1 | 1 |
HSTL_II | 0 | 1 | 1 | 1 | 1 |
HSTL_III | 0 | 1 | 1 | 1 | 1 |
HSTL_III_18 | 0 | 1 | 1 | 1 | 1 |
HSTL_III_DCI | 0 | 1 | 1 | 1 | 1 |
HSTL_III_DCI_18 | 0 | 1 | 1 | 1 | 1 |
HSTL_II_18 | 0 | 1 | 1 | 1 | 1 |
HSTL_II_DCI | 0 | 1 | 1 | 1 | 1 |
HSTL_II_DCI_18 | 0 | 1 | 1 | 1 | 1 |
HSTL_IV | 0 | 1 | 1 | 1 | 1 |
HSTL_IV_18 | 0 | 1 | 1 | 1 | 1 |
HSTL_IV_DCI | 0 | 0 | 0 | 0 | 0 |
HSTL_IV_DCI_18 | 0 | 0 | 0 | 0 | 0 |
HSTL_I_18 | 0 | 1 | 1 | 1 | 1 |
HSTL_I_DCI | 0 | 1 | 1 | 1 | 1 |
HSTL_I_DCI_18 | 0 | 1 | 1 | 1 | 1 |
LVCMOS15.FAST | 1 | 1 | 1 | 1 | 1 |
LVCMOS15.SLOW | 0 | 0 | 0 | 0 | 0 |
LVCMOS18.FAST | 1 | 1 | 1 | 1 | 1 |
LVCMOS18.SLOW | 0 | 0 | 0 | 0 | 0 |
LVCMOS25.FAST | 1 | 1 | 1 | 1 | 1 |
LVCMOS25.SLOW | 0 | 0 | 0 | 0 | 0 |
LVCMOS33.FAST | 1 | 1 | 1 | 1 | 1 |
LVCMOS33.SLOW | 0 | 0 | 0 | 0 | 0 |
LVDCI_15 | 1 | 1 | 1 | 1 | 1 |
LVDCI_18 | 1 | 1 | 1 | 1 | 1 |
LVDCI_25 | 1 | 1 | 1 | 1 | 1 |
LVDCI_33 | 1 | 1 | 1 | 1 | 1 |
LVDCI_DV2_15 | 1 | 1 | 1 | 1 | 1 |
LVDCI_DV2_18 | 1 | 1 | 1 | 1 | 1 |
LVDCI_DV2_25 | 1 | 1 | 1 | 1 | 1 |
LVPECL_25 | 0 | 1 | 1 | 0 | 1 |
LVTTL.FAST | 1 | 1 | 1 | 1 | 1 |
LVTTL.SLOW | 0 | 0 | 0 | 0 | 0 |
PCI33_3 | 0 | 0 | 0 | 0 | 0 |
PCI66_3 | 0 | 0 | 0 | 0 | 0 |
PCIX | 0 | 1 | 1 | 1 | 1 |
SSTL18_I | 0 | 1 | 1 | 0 | 1 |
SSTL18_II | 0 | 1 | 1 | 0 | 1 |
SSTL18_II_DCI | 1 | 1 | 1 | 0 | 1 |
SSTL18_I_DCI | 1 | 1 | 1 | 1 | 1 |
SSTL2_I | 1 | 1 | 1 | 1 | 1 |
SSTL2_II | 1 | 1 | 1 | 1 | 1 |
SSTL2_II_DCI | 1 | 1 | 1 | 1 | 1 |
SSTL2_I_DCI | 1 | 1 | 1 | 1 | 1 |
VR | 1 | 1 | 1 | 1 | 1 |
Name | IOSTD:V2P:OUTPUT_MISC | |
---|---|---|
[1] | [0] | |
BLVDS_25 | 0 | 0 |
GTL | 0 | 1 |
GTLP | 0 | 1 |
GTLP_DCI | 0 | 1 |
GTL_DCI | 1 | 1 |
HSLVDCI_15 | 0 | 0 |
HSLVDCI_18 | 0 | 0 |
HSLVDCI_25 | 0 | 0 |
HSLVDCI_33 | 0 | 0 |
HSTL_I | 0 | 0 |
HSTL_II | 0 | 0 |
HSTL_III | 1 | 0 |
HSTL_III_18 | 1 | 0 |
HSTL_III_DCI | 1 | 0 |
HSTL_III_DCI_18 | 1 | 0 |
HSTL_II_18 | 0 | 0 |
HSTL_II_DCI | 1 | 0 |
HSTL_II_DCI_18 | 1 | 0 |
HSTL_IV | 1 | 0 |
HSTL_IV_18 | 1 | 0 |
HSTL_IV_DCI | 1 | 1 |
HSTL_IV_DCI_18 | 1 | 1 |
HSTL_I_18 | 0 | 0 |
HSTL_I_DCI | 0 | 0 |
HSTL_I_DCI_18 | 0 | 0 |
LVCMOS15 | 0 | 0 |
LVCMOS18 | 0 | 0 |
LVCMOS25 | 0 | 0 |
LVCMOS33 | 0 | 0 |
LVDCI_15 | 0 | 0 |
LVDCI_18 | 0 | 0 |
LVDCI_25 | 0 | 0 |
LVDCI_33 | 0 | 0 |
LVDCI_DV2_15 | 0 | 0 |
LVDCI_DV2_18 | 0 | 0 |
LVDCI_DV2_25 | 0 | 0 |
LVPECL_25 | 0 | 0 |
LVTTL | 0 | 0 |
PCI33_3 | 0 | 0 |
PCI66_3 | 0 | 0 |
PCIX | 0 | 0 |
SSTL18_I | 0 | 0 |
SSTL18_II | 0 | 0 |
SSTL18_II_DCI | 0 | 0 |
SSTL18_I_DCI | 0 | 0 |
SSTL2_I | 0 | 0 |
SSTL2_II | 0 | 0 |
SSTL2_II_DCI | 0 | 1 |
SSTL2_I_DCI | 0 | 0 |
Name | IOSTD:V2P:OUTPUT_DIFF | |||
---|---|---|---|---|
[3] | [2] | [1] | [0] | |
LDT_25 | 1 | 0 | 1 | 0 |
LVDSEXT_25 | 0 | 1 | 1 | 0 |
LVDSEXT_25_DCI | 0 | 1 | 1 | 0 |
LVDS_25 | 0 | 0 | 1 | 0 |
LVDS_25_DCI | 0 | 0 | 1 | 0 |
OFF | 0 | 0 | 0 | 0 |
TERM | 0 | 0 | 0 | 1 |
ULVDS_25 | 1 | 0 | 1 | 0 |
IOBS.V2P.T.L1
IOB0:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB2:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB2:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB1:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB2:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB2:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
Inverted | ~[0] |
IOB0:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
---|---|---|---|
IOB2:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 21, 10] |
---|---|
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB2:DISABLE_GTS | [0, 7, 11] |
Non-inverted | [0] |
IOB2:OUTPUT_DIFF | [0, 9, 11] | [0, 6, 9] | [0, 3, 9] | [0, 12, 9] |
---|---|---|---|---|
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:IBUF_MODE | [0, 18, 6] | [0, 21, 6] | [0, 18, 7] |
---|---|---|---|
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
CMOS | 1 | 1 | 1 |
IOBS.V2P.T.L1.ALT
IOB0:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB2:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB2:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB1:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB2:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB2:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
Inverted | ~[0] |
IOB2:IBUF_MODE | [0, 4, 10] | [0, 7, 8] | [0, 4, 6] |
---|---|---|---|
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 21, 10] |
---|---|
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB2:DISABLE_GTS | [0, 7, 11] |
Non-inverted | [0] |
IOB0:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB1:OUTPUT_DIFF | [0, 17, 8] | [0, 12, 9] | [0, 9, 11] | [0, 21, 11] |
---|---|---|---|---|
Non-inverted | [3] | [2] | [1] | [0] |
IOBS.V2P.T.R1
IOB0:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB2:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB2:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB1:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB2:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB2:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
Inverted | ~[0] |
IOB2:IBUF_MODE | [0, 4, 10] | [0, 7, 8] | [0, 4, 6] |
---|---|---|---|
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 21, 10] |
---|---|
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB2:DISABLE_GTS | [0, 7, 11] |
Non-inverted | [0] |
IOB0:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB1:OUTPUT_DIFF | [0, 17, 8] | [0, 12, 9] | [0, 9, 11] | [0, 21, 11] |
---|---|---|---|---|
Non-inverted | [3] | [2] | [1] | [0] |
IOBS.V2P.T.R1.ALT
IOB0:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB2:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB2:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB1:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB2:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB2:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
Inverted | ~[0] |
IOB0:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
---|---|---|---|
IOB2:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 21, 10] |
---|---|
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB2:DISABLE_GTS | [0, 7, 11] |
Non-inverted | [0] |
IOB2:OUTPUT_DIFF | [0, 9, 11] | [0, 6, 9] | [0, 3, 9] | [0, 12, 9] |
---|---|---|---|---|
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:IBUF_MODE | [0, 18, 6] | [0, 21, 6] | [0, 18, 7] |
---|---|---|---|
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
CMOS | 1 | 1 | 1 |
IOBS.V2P.T.L2
IOB0:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB2:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
IOB3:PDRIVE | [1, 19, 9] | [1, 19, 7] | [1, 19, 8] | [1, 16, 6] |
IOB4:PDRIVE | [1, 11, 9] | [1, 11, 7] | [1, 11, 8] | [1, 8, 8] |
IOB5:PDRIVE | [1, 5, 11] | [1, 5, 7] | [1, 5, 10] | [1, 0, 8] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB2:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
IOB3:NDRIVE | [1, 19, 11] | [1, 19, 10] | [1, 19, 6] | [1, 16, 7] | [1, 16, 10] |
IOB4:NDRIVE | [1, 11, 11] | [1, 11, 10] | [1, 11, 6] | [1, 8, 6] | [1, 8, 11] |
IOB5:NDRIVE | [1, 5, 9] | [1, 5, 6] | [1, 5, 8] | [1, 0, 6] | [1, 0, 9] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB1:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB2:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB2:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
IOB3:OUTPUT_ENABLE | [1, 21, 8] | [1, 21, 7] |
IOB3:OUTPUT_MISC | [1, 16, 11] | [1, 16, 9] |
IOB4:OUTPUT_ENABLE | [1, 13, 8] | [1, 13, 6] |
IOB4:OUTPUT_MISC | [1, 8, 10] | [1, 8, 9] |
IOB5:OUTPUT_ENABLE | [1, 7, 10] | [1, 7, 6] |
IOB5:OUTPUT_MISC | [1, 0, 10] | [1, 0, 11] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
IOB3:SLEW | [1, 17, 9] | [1, 17, 10] | [1, 16, 8] | [1, 17, 6] | [1, 17, 7] |
IOB4:SLEW | [1, 9, 8] | [1, 9, 6] | [1, 8, 7] | [1, 9, 10] | [1, 9, 7] |
IOB5:SLEW | [1, 3, 8] | [1, 3, 6] | [1, 0, 7] | [1, 3, 7] | [1, 3, 10] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
IOB3:DCIUPDATEMODE_ASREQUIRED | [1, 17, 11] |
IOB4:DCIUPDATEMODE_ASREQUIRED | [1, 9, 9] |
IOB5:DCIUPDATEMODE_ASREQUIRED | [1, 3, 11] |
Inverted | ~[0] |
IOB0:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
IOB3:PULL | [1, 18, 8] | [1, 18, 9] | [1, 18, 10] |
IOB4:PULL | [1, 10, 6] | [1, 10, 9] | [1, 10, 10] |
IOB5:PULL | [1, 4, 7] | [1, 4, 8] | [1, 4, 9] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB1:OUTPUT_DIFF | [0, 17, 8] | [0, 12, 9] | [0, 9, 11] | [0, 21, 11] |
---|---|---|---|---|
IOB3:OUTPUT_DIFF | [0, 3, 9] | [1, 21, 11] | [1, 17, 8] | [0, 6, 9] |
IOB5:OUTPUT_DIFF | [1, 9, 11] | [1, 6, 9] | [1, 3, 9] | [1, 12, 9] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
IOB3:DCI_MODE | [1, 18, 11] | [1, 20, 7] | [1, 20, 10] | [1, 20, 11] |
IOB4:DCI_MODE | [1, 10, 11] | [1, 12, 6] | [1, 12, 7] | [1, 12, 10] |
IOB5:DCI_MODE | [1, 4, 11] | [1, 6, 6] | [1, 6, 8] | [1, 6, 10] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
IOB2:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
IOB3:IBUF_MODE | [1, 18, 6] | [1, 18, 7] | [1, 21, 6] |
IOB4:IBUF_MODE | [1, 10, 8] | [1, 10, 7] | [1, 13, 10] |
IOB5:IBUF_MODE | [1, 4, 10] | [1, 4, 6] | [1, 7, 8] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 21, 10] |
---|---|
IOB0:VR | [0, 20, 8] |
IOB1:BREFCLK_ENABLE | [0, 12, 11] |
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB1:VR | [0, 12, 8] |
IOB2:DISABLE_GTS | [0, 7, 11] |
IOB3:DISABLE_GTS | [1, 21, 10] |
IOB4:DISABLE_GTS | [1, 13, 11] |
IOB5:DISABLE_GTS | [1, 7, 11] |
IOB5:VREF | [1, 7, 7] |
Non-inverted | [0] |
IOBS.V2P.T.R2
IOB0:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB2:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
IOB3:PDRIVE | [1, 19, 9] | [1, 19, 7] | [1, 19, 8] | [1, 16, 6] |
IOB4:PDRIVE | [1, 11, 9] | [1, 11, 7] | [1, 11, 8] | [1, 8, 8] |
IOB5:PDRIVE | [1, 5, 11] | [1, 5, 7] | [1, 5, 10] | [1, 0, 8] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB2:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
IOB3:NDRIVE | [1, 19, 11] | [1, 19, 10] | [1, 19, 6] | [1, 16, 7] | [1, 16, 10] |
IOB4:NDRIVE | [1, 11, 11] | [1, 11, 10] | [1, 11, 6] | [1, 8, 6] | [1, 8, 11] |
IOB5:NDRIVE | [1, 5, 9] | [1, 5, 6] | [1, 5, 8] | [1, 0, 6] | [1, 0, 9] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB1:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB2:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB2:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
IOB3:OUTPUT_ENABLE | [1, 21, 8] | [1, 21, 7] |
IOB3:OUTPUT_MISC | [1, 16, 11] | [1, 16, 9] |
IOB4:OUTPUT_ENABLE | [1, 13, 8] | [1, 13, 6] |
IOB4:OUTPUT_MISC | [1, 8, 10] | [1, 8, 9] |
IOB5:OUTPUT_ENABLE | [1, 7, 10] | [1, 7, 6] |
IOB5:OUTPUT_MISC | [1, 0, 10] | [1, 0, 11] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
IOB3:SLEW | [1, 17, 9] | [1, 17, 10] | [1, 16, 8] | [1, 17, 6] | [1, 17, 7] |
IOB4:SLEW | [1, 9, 8] | [1, 9, 6] | [1, 8, 7] | [1, 9, 10] | [1, 9, 7] |
IOB5:SLEW | [1, 3, 8] | [1, 3, 6] | [1, 0, 7] | [1, 3, 7] | [1, 3, 10] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
IOB3:DCIUPDATEMODE_ASREQUIRED | [1, 17, 11] |
IOB4:DCIUPDATEMODE_ASREQUIRED | [1, 9, 9] |
IOB5:DCIUPDATEMODE_ASREQUIRED | [1, 3, 11] |
Inverted | ~[0] |
IOB0:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
IOB3:PULL | [1, 18, 8] | [1, 18, 9] | [1, 18, 10] |
IOB4:PULL | [1, 10, 6] | [1, 10, 9] | [1, 10, 10] |
IOB5:PULL | [1, 4, 7] | [1, 4, 8] | [1, 4, 9] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB1:OUTPUT_DIFF | [0, 17, 8] | [0, 12, 9] | [0, 9, 11] | [0, 21, 11] |
---|---|---|---|---|
IOB3:OUTPUT_DIFF | [0, 3, 9] | [1, 21, 11] | [1, 17, 8] | [0, 6, 9] |
IOB5:OUTPUT_DIFF | [1, 9, 11] | [1, 6, 9] | [1, 3, 9] | [1, 12, 9] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
IOB3:DCI_MODE | [1, 18, 11] | [1, 20, 7] | [1, 20, 10] | [1, 20, 11] |
IOB4:DCI_MODE | [1, 10, 11] | [1, 12, 6] | [1, 12, 7] | [1, 12, 10] |
IOB5:DCI_MODE | [1, 4, 11] | [1, 6, 6] | [1, 6, 8] | [1, 6, 10] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
IOB2:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
IOB3:IBUF_MODE | [1, 18, 6] | [1, 18, 7] | [1, 21, 6] |
IOB4:IBUF_MODE | [1, 10, 8] | [1, 10, 7] | [1, 13, 10] |
IOB5:IBUF_MODE | [1, 4, 10] | [1, 4, 6] | [1, 7, 8] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 21, 10] |
---|---|
IOB0:VREF | [0, 21, 9] |
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB2:DISABLE_GTS | [0, 7, 11] |
IOB3:DISABLE_GTS | [1, 21, 10] |
IOB4:DISABLE_GTS | [1, 13, 11] |
IOB4:VR | [1, 12, 8] |
IOB5:BREFCLK_ENABLE | [1, 6, 11] |
IOB5:DISABLE_GTS | [1, 7, 11] |
IOB5:VR | [1, 6, 7] |
Non-inverted | [0] |
IOBS.V2P.T.R2.CLK
IOBS.V2P.T.R2.CLK bittile 1 | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Row | Column | |||||||||||||||||||||
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | |
0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB3:PDRIVE[0] | IOB3:SLEW[1] | IOB3:IBUF_MODE[2] | ~IOB3:NDRIVE[2] | - | IOB3:IBUF_MODE[0] |
7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB3:NDRIVE[1] | IOB3:SLEW[0] | IOB3:IBUF_MODE[1] | IOB3:PDRIVE[2] | IOB3:DCI_MODE[2] | IOB3:OUTPUT_ENABLE[0] |
8 | - | - | - | - | - | - | - | BREFCLK_INT:ENABLE[1] | - | - | - | - | - | - | - | - | IOB3:SLEW[2] | IOB3:OUTPUT_DIFF[1] | IOB3:PULL[2] | ~IOB3:PDRIVE[1] | - | IOB3:OUTPUT_ENABLE[1] |
9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB3:OUTPUT_MISC[0] | IOB3:SLEW[4] | IOB3:PULL[1] | IOB3:PDRIVE[3] | - | - |
10 | - | - | - | - | BREFCLK_INT:ENABLE[0] | - | - | - | - | - | - | - | - | - | - | - | IOB3:NDRIVE[0] | IOB3:SLEW[3] | IOB3:PULL[0] | IOB3:NDRIVE[3] | IOB3:DCI_MODE[1] | IOB3:DISABLE_GTS |
11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB3:OUTPUT_MISC[1] | ~IOB3:DCIUPDATEMODE_ASREQUIRED | IOB3:DCI_MODE[3] | IOB3:NDRIVE[4] | IOB3:DCI_MODE[0] | IOB3:OUTPUT_DIFF[2] |
IOB0:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB2:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
IOB3:PDRIVE | [1, 19, 9] | [1, 19, 7] | [1, 19, 8] | [1, 16, 6] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB2:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
IOB3:NDRIVE | [1, 19, 11] | [1, 19, 10] | [1, 19, 6] | [1, 16, 7] | [1, 16, 10] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
BREFCLK_INT:ENABLE | [1, 7, 8] | [1, 4, 10] |
---|---|---|
IOB0:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
IOB0:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB1:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB2:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB2:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
IOB3:OUTPUT_ENABLE | [1, 21, 8] | [1, 21, 7] |
IOB3:OUTPUT_MISC | [1, 16, 11] | [1, 16, 9] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
IOB3:SLEW | [1, 17, 9] | [1, 17, 10] | [1, 16, 8] | [1, 17, 6] | [1, 17, 7] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
IOB3:DCIUPDATEMODE_ASREQUIRED | [1, 17, 11] |
Inverted | ~[0] |
IOB0:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
IOB3:PULL | [1, 18, 8] | [1, 18, 9] | [1, 18, 10] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB1:OUTPUT_DIFF | [0, 17, 8] | [0, 12, 9] | [0, 9, 11] | [0, 21, 11] |
---|---|---|---|---|
IOB3:OUTPUT_DIFF | [0, 3, 9] | [1, 21, 11] | [1, 17, 8] | [0, 6, 9] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
IOB3:DCI_MODE | [1, 18, 11] | [1, 20, 7] | [1, 20, 10] | [1, 20, 11] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
IOB2:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
IOB3:IBUF_MODE | [1, 18, 6] | [1, 18, 7] | [1, 21, 6] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 21, 10] |
---|---|
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB2:DISABLE_GTS | [0, 7, 11] |
IOB3:DISABLE_GTS | [1, 21, 10] |
Non-inverted | [0] |
IOBS.V2P.R.B2
IOB0:OUTPUT_ENABLE | [1, 3, 70] | [1, 2, 71] |
---|---|---|
IOB0:OUTPUT_MISC | [1, 3, 61] | [1, 2, 61] |
IOB1:OUTPUT_ENABLE | [1, 3, 43] | [1, 2, 44] |
IOB1:OUTPUT_MISC | [1, 3, 34] | [1, 2, 34] |
IOB2:OUTPUT_ENABLE | [1, 3, 16] | [1, 2, 17] |
IOB2:OUTPUT_MISC | [1, 3, 7] | [1, 2, 7] |
IOB3:OUTPUT_ENABLE | [0, 3, 70] | [0, 2, 71] |
IOB3:OUTPUT_MISC | [0, 3, 61] | [0, 2, 61] |
IOB4:OUTPUT_ENABLE | [0, 3, 43] | [0, 2, 44] |
IOB4:OUTPUT_MISC | [0, 3, 34] | [0, 2, 34] |
IOB5:OUTPUT_ENABLE | [0, 3, 16] | [0, 2, 17] |
IOB5:OUTPUT_MISC | [0, 3, 7] | [0, 2, 7] |
Non-inverted | [1] | [0] |
IOB0:NDRIVE | [1, 2, 66] | [1, 2, 65] | [1, 2, 64] | [1, 2, 63] | [1, 2, 62] |
---|---|---|---|---|---|
IOB1:NDRIVE | [1, 2, 39] | [1, 2, 38] | [1, 2, 37] | [1, 2, 36] | [1, 2, 35] |
IOB2:NDRIVE | [1, 2, 12] | [1, 2, 11] | [1, 2, 10] | [1, 2, 9] | [1, 2, 8] |
IOB3:NDRIVE | [0, 2, 66] | [0, 2, 65] | [0, 2, 64] | [0, 2, 63] | [0, 2, 62] |
IOB4:NDRIVE | [0, 2, 39] | [0, 2, 38] | [0, 2, 37] | [0, 2, 36] | [0, 2, 35] |
IOB5:NDRIVE | [0, 2, 12] | [0, 2, 11] | [0, 2, 10] | [0, 2, 9] | [0, 2, 8] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:IBUF_MODE | [1, 3, 69] | [1, 2, 69] | [1, 2, 70] |
---|---|---|---|
IOB1:IBUF_MODE | [1, 3, 42] | [1, 2, 42] | [1, 2, 43] |
IOB2:IBUF_MODE | [1, 3, 15] | [1, 2, 15] | [1, 2, 16] |
IOB3:IBUF_MODE | [0, 3, 69] | [0, 2, 69] | [0, 2, 70] |
IOB4:IBUF_MODE | [0, 3, 42] | [0, 2, 42] | [0, 2, 43] |
IOB5:IBUF_MODE | [0, 3, 15] | [0, 2, 15] | [0, 2, 16] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [1, 2, 72] |
---|---|
IOB0:VREF | [1, 3, 71] |
IOB1:DISABLE_GTS | [1, 2, 45] |
IOB2:DISABLE_GTS | [1, 2, 18] |
IOB3:DISABLE_GTS | [0, 2, 72] |
IOB4:DISABLE_GTS | [0, 2, 45] |
IOB4:VR | [0, 3, 48] |
IOB5:DISABLE_GTS | [0, 2, 18] |
IOB5:VR | [0, 3, 21] |
Non-inverted | [0] |
IOB0:DCI_MODE | [1, 2, 67] | [1, 2, 75] | [1, 3, 74] | [1, 2, 74] |
---|---|---|---|---|
IOB1:DCI_MODE | [1, 2, 40] | [1, 2, 48] | [1, 3, 47] | [1, 2, 47] |
IOB2:DCI_MODE | [1, 2, 13] | [1, 2, 21] | [1, 3, 20] | [1, 2, 20] |
IOB3:DCI_MODE | [0, 2, 67] | [0, 2, 75] | [0, 3, 74] | [0, 2, 74] |
IOB4:DCI_MODE | [0, 2, 40] | [0, 2, 48] | [0, 3, 47] | [0, 2, 47] |
IOB5:DCI_MODE | [0, 2, 13] | [0, 2, 21] | [0, 3, 20] | [0, 2, 20] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB1:OUTPUT_DIFF | [1, 2, 60] | [1, 2, 46] | [1, 2, 33] | [1, 2, 73] |
---|---|---|---|---|
IOB3:OUTPUT_DIFF | [1, 2, 6] | [0, 2, 73] | [0, 2, 60] | [1, 2, 19] |
IOB5:OUTPUT_DIFF | [0, 2, 33] | [0, 2, 19] | [0, 2, 6] | [0, 2, 46] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:SLEW | [1, 3, 58] | [1, 3, 62] | [1, 2, 58] | [1, 2, 59] | [1, 3, 59] |
---|---|---|---|---|---|
IOB1:SLEW | [1, 3, 31] | [1, 3, 35] | [1, 2, 31] | [1, 2, 32] | [1, 3, 32] |
IOB2:SLEW | [1, 3, 4] | [1, 3, 8] | [1, 2, 4] | [1, 2, 5] | [1, 3, 5] |
IOB3:SLEW | [0, 3, 58] | [0, 3, 62] | [0, 2, 58] | [0, 2, 59] | [0, 3, 59] |
IOB4:SLEW | [0, 3, 31] | [0, 3, 35] | [0, 2, 31] | [0, 2, 32] | [0, 3, 32] |
IOB5:SLEW | [0, 3, 4] | [0, 3, 8] | [0, 2, 4] | [0, 2, 5] | [0, 3, 5] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [1, 3, 60] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [1, 3, 33] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [1, 3, 6] |
IOB3:DCIUPDATEMODE_ASREQUIRED | [0, 3, 60] |
IOB4:DCIUPDATEMODE_ASREQUIRED | [0, 3, 33] |
IOB5:DCIUPDATEMODE_ASREQUIRED | [0, 3, 6] |
Inverted | ~[0] |
IOB0:PDRIVE | [1, 3, 66] | [1, 3, 65] | [1, 3, 64] | [1, 3, 63] |
---|---|---|---|---|
IOB1:PDRIVE | [1, 3, 39] | [1, 3, 38] | [1, 3, 37] | [1, 3, 36] |
IOB2:PDRIVE | [1, 3, 12] | [1, 3, 11] | [1, 3, 10] | [1, 3, 9] |
IOB3:PDRIVE | [0, 3, 66] | [0, 3, 65] | [0, 3, 64] | [0, 3, 63] |
IOB4:PDRIVE | [0, 3, 39] | [0, 3, 38] | [0, 3, 37] | [0, 3, 36] |
IOB5:PDRIVE | [0, 3, 12] | [0, 3, 11] | [0, 3, 10] | [0, 3, 9] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:PULL | [1, 3, 68] | [1, 2, 68] | [1, 3, 67] |
---|---|---|---|
IOB1:PULL | [1, 3, 41] | [1, 2, 41] | [1, 3, 40] |
IOB2:PULL | [1, 3, 14] | [1, 2, 14] | [1, 3, 13] |
IOB3:PULL | [0, 3, 68] | [0, 2, 68] | [0, 3, 67] |
IOB4:PULL | [0, 3, 41] | [0, 2, 41] | [0, 3, 40] |
IOB5:PULL | [0, 3, 14] | [0, 2, 14] | [0, 3, 13] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOBS.V2P.R.T2
IOB0:OUTPUT_ENABLE | [1, 3, 70] | [1, 2, 71] |
---|---|---|
IOB0:OUTPUT_MISC | [1, 3, 61] | [1, 2, 61] |
IOB1:OUTPUT_ENABLE | [1, 3, 43] | [1, 2, 44] |
IOB1:OUTPUT_MISC | [1, 3, 34] | [1, 2, 34] |
IOB2:OUTPUT_ENABLE | [1, 3, 16] | [1, 2, 17] |
IOB2:OUTPUT_MISC | [1, 3, 7] | [1, 2, 7] |
IOB3:OUTPUT_ENABLE | [0, 3, 70] | [0, 2, 71] |
IOB3:OUTPUT_MISC | [0, 3, 61] | [0, 2, 61] |
IOB4:OUTPUT_ENABLE | [0, 3, 43] | [0, 2, 44] |
IOB4:OUTPUT_MISC | [0, 3, 34] | [0, 2, 34] |
IOB5:OUTPUT_ENABLE | [0, 3, 16] | [0, 2, 17] |
IOB5:OUTPUT_MISC | [0, 3, 7] | [0, 2, 7] |
Non-inverted | [1] | [0] |
IOB0:NDRIVE | [1, 2, 66] | [1, 2, 65] | [1, 2, 64] | [1, 2, 63] | [1, 2, 62] |
---|---|---|---|---|---|
IOB1:NDRIVE | [1, 2, 39] | [1, 2, 38] | [1, 2, 37] | [1, 2, 36] | [1, 2, 35] |
IOB2:NDRIVE | [1, 2, 12] | [1, 2, 11] | [1, 2, 10] | [1, 2, 9] | [1, 2, 8] |
IOB3:NDRIVE | [0, 2, 66] | [0, 2, 65] | [0, 2, 64] | [0, 2, 63] | [0, 2, 62] |
IOB4:NDRIVE | [0, 2, 39] | [0, 2, 38] | [0, 2, 37] | [0, 2, 36] | [0, 2, 35] |
IOB5:NDRIVE | [0, 2, 12] | [0, 2, 11] | [0, 2, 10] | [0, 2, 9] | [0, 2, 8] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:IBUF_MODE | [1, 3, 69] | [1, 2, 69] | [1, 2, 70] |
---|---|---|---|
IOB1:IBUF_MODE | [1, 3, 42] | [1, 2, 42] | [1, 2, 43] |
IOB2:IBUF_MODE | [1, 3, 15] | [1, 2, 15] | [1, 2, 16] |
IOB3:IBUF_MODE | [0, 3, 69] | [0, 2, 69] | [0, 2, 70] |
IOB4:IBUF_MODE | [0, 3, 42] | [0, 2, 42] | [0, 2, 43] |
IOB5:IBUF_MODE | [0, 3, 15] | [0, 2, 15] | [0, 2, 16] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [1, 2, 72] |
---|---|
IOB0:VR | [1, 3, 75] |
IOB0:VREF | [1, 3, 71] |
IOB1:DISABLE_GTS | [1, 2, 45] |
IOB1:VR | [1, 3, 48] |
IOB2:DISABLE_GTS | [1, 2, 18] |
IOB3:DISABLE_GTS | [0, 2, 72] |
IOB4:DISABLE_GTS | [0, 2, 45] |
IOB5:DISABLE_GTS | [0, 2, 18] |
Non-inverted | [0] |
IOB0:DCI_MODE | [1, 2, 67] | [1, 2, 75] | [1, 3, 74] | [1, 2, 74] |
---|---|---|---|---|
IOB1:DCI_MODE | [1, 2, 40] | [1, 2, 48] | [1, 3, 47] | [1, 2, 47] |
IOB2:DCI_MODE | [1, 2, 13] | [1, 2, 21] | [1, 3, 20] | [1, 2, 20] |
IOB3:DCI_MODE | [0, 2, 67] | [0, 2, 75] | [0, 3, 74] | [0, 2, 74] |
IOB4:DCI_MODE | [0, 2, 40] | [0, 2, 48] | [0, 3, 47] | [0, 2, 47] |
IOB5:DCI_MODE | [0, 2, 13] | [0, 2, 21] | [0, 3, 20] | [0, 2, 20] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB1:OUTPUT_DIFF | [1, 2, 60] | [1, 2, 46] | [1, 2, 33] | [1, 2, 73] |
---|---|---|---|---|
IOB3:OUTPUT_DIFF | [1, 2, 6] | [0, 2, 73] | [0, 2, 60] | [1, 2, 19] |
IOB5:OUTPUT_DIFF | [0, 2, 33] | [0, 2, 19] | [0, 2, 6] | [0, 2, 46] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:SLEW | [1, 3, 58] | [1, 3, 62] | [1, 2, 58] | [1, 2, 59] | [1, 3, 59] |
---|---|---|---|---|---|
IOB1:SLEW | [1, 3, 31] | [1, 3, 35] | [1, 2, 31] | [1, 2, 32] | [1, 3, 32] |
IOB2:SLEW | [1, 3, 4] | [1, 3, 8] | [1, 2, 4] | [1, 2, 5] | [1, 3, 5] |
IOB3:SLEW | [0, 3, 58] | [0, 3, 62] | [0, 2, 58] | [0, 2, 59] | [0, 3, 59] |
IOB4:SLEW | [0, 3, 31] | [0, 3, 35] | [0, 2, 31] | [0, 2, 32] | [0, 3, 32] |
IOB5:SLEW | [0, 3, 4] | [0, 3, 8] | [0, 2, 4] | [0, 2, 5] | [0, 3, 5] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [1, 3, 60] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [1, 3, 33] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [1, 3, 6] |
IOB3:DCIUPDATEMODE_ASREQUIRED | [0, 3, 60] |
IOB4:DCIUPDATEMODE_ASREQUIRED | [0, 3, 33] |
IOB5:DCIUPDATEMODE_ASREQUIRED | [0, 3, 6] |
Inverted | ~[0] |
IOB0:PDRIVE | [1, 3, 66] | [1, 3, 65] | [1, 3, 64] | [1, 3, 63] |
---|---|---|---|---|
IOB1:PDRIVE | [1, 3, 39] | [1, 3, 38] | [1, 3, 37] | [1, 3, 36] |
IOB2:PDRIVE | [1, 3, 12] | [1, 3, 11] | [1, 3, 10] | [1, 3, 9] |
IOB3:PDRIVE | [0, 3, 66] | [0, 3, 65] | [0, 3, 64] | [0, 3, 63] |
IOB4:PDRIVE | [0, 3, 39] | [0, 3, 38] | [0, 3, 37] | [0, 3, 36] |
IOB5:PDRIVE | [0, 3, 12] | [0, 3, 11] | [0, 3, 10] | [0, 3, 9] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:PULL | [1, 3, 68] | [1, 2, 68] | [1, 3, 67] |
---|---|---|---|
IOB1:PULL | [1, 3, 41] | [1, 2, 41] | [1, 3, 40] |
IOB2:PULL | [1, 3, 14] | [1, 2, 14] | [1, 3, 13] |
IOB3:PULL | [0, 3, 68] | [0, 2, 68] | [0, 3, 67] |
IOB4:PULL | [0, 3, 41] | [0, 2, 41] | [0, 3, 40] |
IOB5:PULL | [0, 3, 14] | [0, 2, 14] | [0, 3, 13] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOBS.V2P.B.L1
IOB0:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB2:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB2:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB1:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB2:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
IOB2:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
Inverted | ~[0] |
IOB0:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DISABLE_GTS | [0, 7, 11] |
---|---|
IOB0:VR | [0, 6, 7] |
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB1:VR | [0, 12, 8] |
IOB2:DISABLE_GTS | [0, 21, 10] |
Non-inverted | [0] |
IOB1:OUTPUT_DIFF | [0, 3, 9] | [0, 12, 9] | [0, 9, 11] | [0, 6, 9] |
---|---|---|---|---|
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB2:IBUF_MODE | [0, 18, 6] | [0, 21, 6] | [0, 18, 7] |
---|---|---|---|
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
CMOS | 1 | 1 | 1 |
IOBS.V2P.B.L1.ALT
IOB0:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB2:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB2:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB1:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB2:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
IOB2:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
Inverted | ~[0] |
IOB0:IBUF_MODE | [0, 4, 10] | [0, 7, 8] | [0, 4, 6] |
---|---|---|---|
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 7, 11] |
---|---|
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB2:DISABLE_GTS | [0, 21, 10] |
Non-inverted | [0] |
IOB2:OUTPUT_DIFF | [0, 9, 11] | [0, 21, 11] | [0, 17, 8] | [0, 12, 9] |
---|---|---|---|---|
Non-inverted | [3] | [2] | [1] | [0] |
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
---|---|---|---|
IOB2:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOBS.V2P.B.R1
IOB0:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB2:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB2:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB1:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB2:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
IOB2:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
Inverted | ~[0] |
IOB0:IBUF_MODE | [0, 4, 10] | [0, 7, 8] | [0, 4, 6] |
---|---|---|---|
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 7, 11] |
---|---|
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB1:VR | [0, 12, 8] |
IOB2:DISABLE_GTS | [0, 21, 10] |
IOB2:VR | [0, 20, 8] |
Non-inverted | [0] |
IOB2:OUTPUT_DIFF | [0, 9, 11] | [0, 21, 11] | [0, 17, 8] | [0, 12, 9] |
---|---|---|---|---|
Non-inverted | [3] | [2] | [1] | [0] |
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
---|---|---|---|
IOB2:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOBS.V2P.B.R1.ALT
IOB0:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB2:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB2:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
IOB1:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB1:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB2:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
IOB2:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB2:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
Inverted | ~[0] |
IOB0:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
---|---|---|---|
IOB1:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB2:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB1:OUTPUT_DIFF | [0, 3, 9] | [0, 12, 9] | [0, 9, 11] | [0, 6, 9] |
---|---|---|---|---|
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB2:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 7, 11] |
---|---|
IOB1:DISABLE_GTS | [0, 13, 11] |
IOB2:DISABLE_GTS | [0, 21, 10] |
Non-inverted | [0] |
IOB2:IBUF_MODE | [0, 18, 6] | [0, 21, 6] | [0, 18, 7] |
---|---|---|---|
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
CMOS | 1 | 1 | 1 |
IOBS.V2P.B.L2
IOB0:PDRIVE | [1, 5, 11] | [1, 5, 7] | [1, 5, 10] | [1, 0, 8] |
---|---|---|---|---|
IOB1:PDRIVE | [1, 11, 9] | [1, 11, 7] | [1, 11, 8] | [1, 8, 8] |
IOB2:PDRIVE | [1, 19, 9] | [1, 19, 7] | [1, 19, 8] | [1, 16, 6] |
IOB3:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
IOB4:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB5:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [1, 5, 9] | [1, 5, 6] | [1, 5, 8] | [1, 0, 6] | [1, 0, 9] |
---|---|---|---|---|---|
IOB1:NDRIVE | [1, 11, 11] | [1, 11, 10] | [1, 11, 6] | [1, 8, 6] | [1, 8, 11] |
IOB2:NDRIVE | [1, 19, 11] | [1, 19, 10] | [1, 19, 6] | [1, 16, 7] | [1, 16, 10] |
IOB3:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
IOB4:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB5:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [1, 7, 10] | [1, 7, 6] |
---|---|---|
IOB0:OUTPUT_MISC | [1, 0, 10] | [1, 0, 11] |
IOB1:OUTPUT_ENABLE | [1, 13, 8] | [1, 13, 6] |
IOB1:OUTPUT_MISC | [1, 8, 10] | [1, 8, 9] |
IOB2:OUTPUT_ENABLE | [1, 21, 8] | [1, 21, 7] |
IOB2:OUTPUT_MISC | [1, 16, 11] | [1, 16, 9] |
IOB3:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB3:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
IOB4:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB4:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB5:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
IOB5:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [1, 3, 8] | [1, 3, 6] | [1, 0, 7] | [1, 3, 7] | [1, 3, 10] |
---|---|---|---|---|---|
IOB1:SLEW | [1, 9, 8] | [1, 9, 6] | [1, 8, 7] | [1, 9, 10] | [1, 9, 7] |
IOB2:SLEW | [1, 17, 9] | [1, 17, 10] | [1, 16, 8] | [1, 17, 6] | [1, 17, 7] |
IOB3:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
IOB4:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB5:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [1, 3, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [1, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [1, 17, 11] |
IOB3:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
IOB4:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB5:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
Inverted | ~[0] |
IOB0:PULL | [1, 4, 7] | [1, 4, 8] | [1, 4, 9] |
---|---|---|---|
IOB1:PULL | [1, 10, 6] | [1, 10, 9] | [1, 10, 10] |
IOB2:PULL | [1, 18, 8] | [1, 18, 9] | [1, 18, 10] |
IOB3:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
IOB4:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB5:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [1, 4, 11] | [1, 6, 6] | [1, 6, 8] | [1, 6, 10] |
---|---|---|---|---|
IOB1:DCI_MODE | [1, 10, 11] | [1, 12, 6] | [1, 12, 7] | [1, 12, 10] |
IOB2:DCI_MODE | [1, 18, 11] | [1, 20, 7] | [1, 20, 10] | [1, 20, 11] |
IOB3:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
IOB4:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB5:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:IBUF_MODE | [1, 4, 10] | [1, 4, 6] | [1, 7, 8] |
---|---|---|---|
IOB1:IBUF_MODE | [1, 10, 8] | [1, 10, 7] | [1, 13, 10] |
IOB2:IBUF_MODE | [1, 18, 6] | [1, 18, 7] | [1, 21, 6] |
IOB3:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
IOB4:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
IOB5:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [1, 7, 11] |
---|---|
IOB0:VREF | [1, 7, 7] |
IOB1:DISABLE_GTS | [1, 13, 11] |
IOB2:DISABLE_GTS | [1, 21, 10] |
IOB3:DISABLE_GTS | [0, 7, 11] |
IOB4:DISABLE_GTS | [0, 13, 11] |
IOB4:VREF | [0, 13, 7] |
IOB5:BREFCLK_ENABLE | [0, 20, 6] |
IOB5:DISABLE_GTS | [0, 21, 10] |
Non-inverted | [0] |
IOB1:OUTPUT_DIFF | [1, 3, 9] | [1, 12, 9] | [1, 9, 11] | [1, 6, 9] |
---|---|---|---|---|
IOB3:OUTPUT_DIFF | [1, 17, 8] | [0, 6, 9] | [0, 3, 9] | [1, 21, 11] |
IOB5:OUTPUT_DIFF | [0, 9, 11] | [0, 21, 11] | [0, 17, 8] | [0, 12, 9] |
Non-inverted | [3] | [2] | [1] | [0] |
IOBS.V2P.B.R2
IOB0:PDRIVE | [1, 5, 11] | [1, 5, 7] | [1, 5, 10] | [1, 0, 8] |
---|---|---|---|---|
IOB1:PDRIVE | [1, 11, 9] | [1, 11, 7] | [1, 11, 8] | [1, 8, 8] |
IOB2:PDRIVE | [1, 19, 9] | [1, 19, 7] | [1, 19, 8] | [1, 16, 6] |
IOB3:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
IOB4:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB5:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [1, 5, 9] | [1, 5, 6] | [1, 5, 8] | [1, 0, 6] | [1, 0, 9] |
---|---|---|---|---|---|
IOB1:NDRIVE | [1, 11, 11] | [1, 11, 10] | [1, 11, 6] | [1, 8, 6] | [1, 8, 11] |
IOB2:NDRIVE | [1, 19, 11] | [1, 19, 10] | [1, 19, 6] | [1, 16, 7] | [1, 16, 10] |
IOB3:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
IOB4:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB5:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:OUTPUT_ENABLE | [1, 7, 10] | [1, 7, 6] |
---|---|---|
IOB0:OUTPUT_MISC | [1, 0, 10] | [1, 0, 11] |
IOB1:OUTPUT_ENABLE | [1, 13, 8] | [1, 13, 6] |
IOB1:OUTPUT_MISC | [1, 8, 10] | [1, 8, 9] |
IOB2:OUTPUT_ENABLE | [1, 21, 8] | [1, 21, 7] |
IOB2:OUTPUT_MISC | [1, 16, 11] | [1, 16, 9] |
IOB3:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB3:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
IOB4:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB4:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB5:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
IOB5:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [1, 3, 8] | [1, 3, 6] | [1, 0, 7] | [1, 3, 7] | [1, 3, 10] |
---|---|---|---|---|---|
IOB1:SLEW | [1, 9, 8] | [1, 9, 6] | [1, 8, 7] | [1, 9, 10] | [1, 9, 7] |
IOB2:SLEW | [1, 17, 9] | [1, 17, 10] | [1, 16, 8] | [1, 17, 6] | [1, 17, 7] |
IOB3:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
IOB4:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB5:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [1, 3, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [1, 9, 9] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [1, 17, 11] |
IOB3:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
IOB4:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB5:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
Inverted | ~[0] |
IOB0:PULL | [1, 4, 7] | [1, 4, 8] | [1, 4, 9] |
---|---|---|---|
IOB1:PULL | [1, 10, 6] | [1, 10, 9] | [1, 10, 10] |
IOB2:PULL | [1, 18, 8] | [1, 18, 9] | [1, 18, 10] |
IOB3:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
IOB4:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB5:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [1, 4, 11] | [1, 6, 6] | [1, 6, 8] | [1, 6, 10] |
---|---|---|---|---|
IOB1:DCI_MODE | [1, 10, 11] | [1, 12, 6] | [1, 12, 7] | [1, 12, 10] |
IOB2:DCI_MODE | [1, 18, 11] | [1, 20, 7] | [1, 20, 10] | [1, 20, 11] |
IOB3:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
IOB4:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB5:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:IBUF_MODE | [1, 4, 10] | [1, 4, 6] | [1, 7, 8] |
---|---|---|---|
IOB1:IBUF_MODE | [1, 10, 8] | [1, 10, 7] | [1, 13, 10] |
IOB2:IBUF_MODE | [1, 18, 6] | [1, 18, 7] | [1, 21, 6] |
IOB3:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
IOB4:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
IOB5:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [1, 7, 11] |
---|---|
IOB1:BREFCLK_ENABLE | [1, 12, 11] |
IOB1:DISABLE_GTS | [1, 13, 11] |
IOB1:VREF | [1, 13, 7] |
IOB2:DISABLE_GTS | [1, 21, 10] |
IOB3:DISABLE_GTS | [0, 7, 11] |
IOB4:DISABLE_GTS | [0, 13, 11] |
IOB5:DISABLE_GTS | [0, 21, 10] |
IOB5:VREF | [0, 21, 9] |
Non-inverted | [0] |
IOB1:OUTPUT_DIFF | [1, 3, 9] | [1, 12, 9] | [1, 9, 11] | [1, 6, 9] |
---|---|---|---|---|
IOB3:OUTPUT_DIFF | [1, 17, 8] | [0, 6, 9] | [0, 3, 9] | [1, 21, 11] |
IOB5:OUTPUT_DIFF | [0, 9, 11] | [0, 21, 11] | [0, 17, 8] | [0, 12, 9] |
Non-inverted | [3] | [2] | [1] | [0] |
IOBS.V2P.B.R2.CLK
IOBS.V2P.B.R2.CLK bittile 1 | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Row | Column | |||||||||||||||||||||
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | |
0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB0:PDRIVE[0] | IOB0:SLEW[1] | IOB0:IBUF_MODE[2] | ~IOB0:NDRIVE[2] | - | IOB0:IBUF_MODE[0] |
7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | ~IOB0:NDRIVE[1] | IOB0:SLEW[0] | IOB0:IBUF_MODE[1] | IOB0:PDRIVE[2] | IOB0:DCI_MODE[2] | IOB0:OUTPUT_ENABLE[0] |
8 | - | - | - | - | - | - | - | - | - | - | BREFCLK_INT:ENABLE[0] | - | - | - | - | - | IOB0:SLEW[2] | IOB1:OUTPUT_DIFF[3] | IOB0:PULL[2] | ~IOB0:PDRIVE[1] | - | IOB0:OUTPUT_ENABLE[1] |
9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:OUTPUT_MISC[0] | IOB0:SLEW[4] | IOB0:PULL[1] | IOB0:PDRIVE[3] | - | - |
10 | - | - | - | - | - | - | - | - | - | - | - | - | - | BREFCLK_INT:ENABLE[1] | - | - | IOB0:NDRIVE[0] | IOB0:SLEW[3] | IOB0:PULL[0] | IOB0:NDRIVE[3] | IOB0:DCI_MODE[1] | IOB0:DISABLE_GTS |
11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | IOB0:OUTPUT_MISC[1] | ~IOB0:DCIUPDATEMODE_ASREQUIRED | IOB0:DCI_MODE[3] | IOB0:NDRIVE[4] | IOB0:DCI_MODE[0] | IOB1:OUTPUT_DIFF[0] |
IOB0:PDRIVE | [1, 19, 9] | [1, 19, 7] | [1, 19, 8] | [1, 16, 6] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 5, 11] | [0, 5, 7] | [0, 5, 10] | [0, 0, 8] |
IOB2:PDRIVE | [0, 11, 9] | [0, 11, 7] | [0, 11, 8] | [0, 8, 8] |
IOB3:PDRIVE | [0, 19, 9] | [0, 19, 7] | [0, 19, 8] | [0, 16, 6] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:NDRIVE | [1, 19, 11] | [1, 19, 10] | [1, 19, 6] | [1, 16, 7] | [1, 16, 10] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 5, 9] | [0, 5, 6] | [0, 5, 8] | [0, 0, 6] | [0, 0, 9] |
IOB2:NDRIVE | [0, 11, 11] | [0, 11, 10] | [0, 11, 6] | [0, 8, 6] | [0, 8, 11] |
IOB3:NDRIVE | [0, 19, 11] | [0, 19, 10] | [0, 19, 6] | [0, 16, 7] | [0, 16, 10] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
BREFCLK_INT:ENABLE | [1, 13, 10] | [1, 10, 8] |
---|---|---|
IOB0:OUTPUT_ENABLE | [1, 21, 8] | [1, 21, 7] |
IOB0:OUTPUT_MISC | [1, 16, 11] | [1, 16, 9] |
IOB1:OUTPUT_ENABLE | [0, 7, 10] | [0, 7, 6] |
IOB1:OUTPUT_MISC | [0, 0, 10] | [0, 0, 11] |
IOB2:OUTPUT_ENABLE | [0, 13, 8] | [0, 13, 6] |
IOB2:OUTPUT_MISC | [0, 8, 10] | [0, 8, 9] |
IOB3:OUTPUT_ENABLE | [0, 21, 8] | [0, 21, 7] |
IOB3:OUTPUT_MISC | [0, 16, 11] | [0, 16, 9] |
Non-inverted | [1] | [0] |
IOB0:SLEW | [1, 17, 9] | [1, 17, 10] | [1, 16, 8] | [1, 17, 6] | [1, 17, 7] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 3, 8] | [0, 3, 6] | [0, 0, 7] | [0, 3, 7] | [0, 3, 10] |
IOB2:SLEW | [0, 9, 8] | [0, 9, 6] | [0, 8, 7] | [0, 9, 10] | [0, 9, 7] |
IOB3:SLEW | [0, 17, 9] | [0, 17, 10] | [0, 16, 8] | [0, 17, 6] | [0, 17, 7] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [1, 17, 11] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 3, 11] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 9, 9] |
IOB3:DCIUPDATEMODE_ASREQUIRED | [0, 17, 11] |
Inverted | ~[0] |
IOB0:PULL | [1, 18, 8] | [1, 18, 9] | [1, 18, 10] |
---|---|---|---|
IOB1:PULL | [0, 4, 7] | [0, 4, 8] | [0, 4, 9] |
IOB2:PULL | [0, 10, 6] | [0, 10, 9] | [0, 10, 10] |
IOB3:PULL | [0, 18, 8] | [0, 18, 9] | [0, 18, 10] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:DCI_MODE | [1, 18, 11] | [1, 20, 7] | [1, 20, 10] | [1, 20, 11] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 4, 11] | [0, 6, 6] | [0, 6, 8] | [0, 6, 10] |
IOB2:DCI_MODE | [0, 10, 11] | [0, 12, 6] | [0, 12, 7] | [0, 12, 10] |
IOB3:DCI_MODE | [0, 18, 11] | [0, 20, 7] | [0, 20, 10] | [0, 20, 11] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:IBUF_MODE | [1, 18, 6] | [1, 18, 7] | [1, 21, 6] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 4, 10] | [0, 4, 6] | [0, 7, 8] |
IOB2:IBUF_MODE | [0, 10, 8] | [0, 10, 7] | [0, 13, 10] |
IOB3:IBUF_MODE | [0, 18, 6] | [0, 18, 7] | [0, 21, 6] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [1, 21, 10] |
---|---|
IOB1:DISABLE_GTS | [0, 7, 11] |
IOB2:DISABLE_GTS | [0, 13, 11] |
IOB3:DISABLE_GTS | [0, 21, 10] |
Non-inverted | [0] |
IOB1:OUTPUT_DIFF | [1, 17, 8] | [0, 6, 9] | [0, 3, 9] | [1, 21, 11] |
---|---|---|---|---|
IOB3:OUTPUT_DIFF | [0, 9, 11] | [0, 21, 11] | [0, 17, 8] | [0, 12, 9] |
Non-inverted | [3] | [2] | [1] | [0] |
IOBS.V2P.L.B2
IOB0:OUTPUT_ENABLE | [0, 3, 16] | [0, 2, 17] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 3, 7] | [0, 2, 7] |
IOB1:OUTPUT_ENABLE | [0, 3, 43] | [0, 2, 44] |
IOB1:OUTPUT_MISC | [0, 3, 34] | [0, 2, 34] |
IOB2:OUTPUT_ENABLE | [0, 3, 70] | [0, 2, 71] |
IOB2:OUTPUT_MISC | [0, 3, 61] | [0, 2, 61] |
IOB3:OUTPUT_ENABLE | [1, 3, 16] | [1, 2, 17] |
IOB3:OUTPUT_MISC | [1, 3, 7] | [1, 2, 7] |
IOB4:OUTPUT_ENABLE | [1, 3, 43] | [1, 2, 44] |
IOB4:OUTPUT_MISC | [1, 3, 34] | [1, 2, 34] |
IOB5:OUTPUT_ENABLE | [1, 3, 70] | [1, 2, 71] |
IOB5:OUTPUT_MISC | [1, 3, 61] | [1, 2, 61] |
Non-inverted | [1] | [0] |
IOB0:NDRIVE | [0, 2, 12] | [0, 2, 11] | [0, 2, 10] | [0, 2, 9] | [0, 2, 8] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 2, 39] | [0, 2, 38] | [0, 2, 37] | [0, 2, 36] | [0, 2, 35] |
IOB2:NDRIVE | [0, 2, 66] | [0, 2, 65] | [0, 2, 64] | [0, 2, 63] | [0, 2, 62] |
IOB3:NDRIVE | [1, 2, 12] | [1, 2, 11] | [1, 2, 10] | [1, 2, 9] | [1, 2, 8] |
IOB4:NDRIVE | [1, 2, 39] | [1, 2, 38] | [1, 2, 37] | [1, 2, 36] | [1, 2, 35] |
IOB5:NDRIVE | [1, 2, 66] | [1, 2, 65] | [1, 2, 64] | [1, 2, 63] | [1, 2, 62] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:IBUF_MODE | [0, 3, 15] | [0, 2, 15] | [0, 2, 16] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 3, 42] | [0, 2, 42] | [0, 2, 43] |
IOB2:IBUF_MODE | [0, 3, 69] | [0, 2, 69] | [0, 2, 70] |
IOB3:IBUF_MODE | [1, 3, 15] | [1, 2, 15] | [1, 2, 16] |
IOB4:IBUF_MODE | [1, 3, 42] | [1, 2, 42] | [1, 2, 43] |
IOB5:IBUF_MODE | [1, 3, 69] | [1, 2, 69] | [1, 2, 70] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 2, 18] |
---|---|
IOB0:VR | [0, 3, 21] |
IOB1:DISABLE_GTS | [0, 2, 45] |
IOB1:VR | [0, 3, 48] |
IOB2:DISABLE_GTS | [0, 2, 72] |
IOB3:DISABLE_GTS | [1, 2, 18] |
IOB4:DISABLE_GTS | [1, 2, 45] |
IOB5:DISABLE_GTS | [1, 2, 72] |
IOB5:VREF | [1, 3, 71] |
Non-inverted | [0] |
IOB0:DCI_MODE | [0, 2, 13] | [0, 2, 21] | [0, 3, 20] | [0, 2, 20] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 2, 40] | [0, 2, 48] | [0, 3, 47] | [0, 2, 47] |
IOB2:DCI_MODE | [0, 2, 67] | [0, 2, 75] | [0, 3, 74] | [0, 2, 74] |
IOB3:DCI_MODE | [1, 2, 13] | [1, 2, 21] | [1, 3, 20] | [1, 2, 20] |
IOB4:DCI_MODE | [1, 2, 40] | [1, 2, 48] | [1, 3, 47] | [1, 2, 47] |
IOB5:DCI_MODE | [1, 2, 67] | [1, 2, 75] | [1, 3, 74] | [1, 2, 74] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:OUTPUT_DIFF | [0, 2, 33] | [0, 2, 19] | [0, 2, 6] | [0, 2, 46] |
---|---|---|---|---|
IOB2:OUTPUT_DIFF | [1, 2, 6] | [0, 2, 73] | [0, 2, 60] | [1, 2, 19] |
IOB4:OUTPUT_DIFF | [1, 2, 60] | [1, 2, 46] | [1, 2, 33] | [1, 2, 73] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:SLEW | [0, 3, 4] | [0, 3, 8] | [0, 2, 4] | [0, 2, 5] | [0, 3, 5] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 3, 31] | [0, 3, 35] | [0, 2, 31] | [0, 2, 32] | [0, 3, 32] |
IOB2:SLEW | [0, 3, 58] | [0, 3, 62] | [0, 2, 58] | [0, 2, 59] | [0, 3, 59] |
IOB3:SLEW | [1, 3, 4] | [1, 3, 8] | [1, 2, 4] | [1, 2, 5] | [1, 3, 5] |
IOB4:SLEW | [1, 3, 31] | [1, 3, 35] | [1, 2, 31] | [1, 2, 32] | [1, 3, 32] |
IOB5:SLEW | [1, 3, 58] | [1, 3, 62] | [1, 2, 58] | [1, 2, 59] | [1, 3, 59] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 3, 6] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 3, 33] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 3, 60] |
IOB3:DCIUPDATEMODE_ASREQUIRED | [1, 3, 6] |
IOB4:DCIUPDATEMODE_ASREQUIRED | [1, 3, 33] |
IOB5:DCIUPDATEMODE_ASREQUIRED | [1, 3, 60] |
Inverted | ~[0] |
IOB0:PDRIVE | [0, 3, 12] | [0, 3, 11] | [0, 3, 10] | [0, 3, 9] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 3, 39] | [0, 3, 38] | [0, 3, 37] | [0, 3, 36] |
IOB2:PDRIVE | [0, 3, 66] | [0, 3, 65] | [0, 3, 64] | [0, 3, 63] |
IOB3:PDRIVE | [1, 3, 12] | [1, 3, 11] | [1, 3, 10] | [1, 3, 9] |
IOB4:PDRIVE | [1, 3, 39] | [1, 3, 38] | [1, 3, 37] | [1, 3, 36] |
IOB5:PDRIVE | [1, 3, 66] | [1, 3, 65] | [1, 3, 64] | [1, 3, 63] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:PULL | [0, 3, 14] | [0, 2, 14] | [0, 3, 13] |
---|---|---|---|
IOB1:PULL | [0, 3, 41] | [0, 2, 41] | [0, 3, 40] |
IOB2:PULL | [0, 3, 68] | [0, 2, 68] | [0, 3, 67] |
IOB3:PULL | [1, 3, 14] | [1, 2, 14] | [1, 3, 13] |
IOB4:PULL | [1, 3, 41] | [1, 2, 41] | [1, 3, 40] |
IOB5:PULL | [1, 3, 68] | [1, 2, 68] | [1, 3, 67] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOBS.V2P.L.T2
IOB0:OUTPUT_ENABLE | [0, 3, 16] | [0, 2, 17] |
---|---|---|
IOB0:OUTPUT_MISC | [0, 3, 7] | [0, 2, 7] |
IOB1:OUTPUT_ENABLE | [0, 3, 43] | [0, 2, 44] |
IOB1:OUTPUT_MISC | [0, 3, 34] | [0, 2, 34] |
IOB2:OUTPUT_ENABLE | [0, 3, 70] | [0, 2, 71] |
IOB2:OUTPUT_MISC | [0, 3, 61] | [0, 2, 61] |
IOB3:OUTPUT_ENABLE | [1, 3, 16] | [1, 2, 17] |
IOB3:OUTPUT_MISC | [1, 3, 7] | [1, 2, 7] |
IOB4:OUTPUT_ENABLE | [1, 3, 43] | [1, 2, 44] |
IOB4:OUTPUT_MISC | [1, 3, 34] | [1, 2, 34] |
IOB5:OUTPUT_ENABLE | [1, 3, 70] | [1, 2, 71] |
IOB5:OUTPUT_MISC | [1, 3, 61] | [1, 2, 61] |
Non-inverted | [1] | [0] |
IOB0:NDRIVE | [0, 2, 12] | [0, 2, 11] | [0, 2, 10] | [0, 2, 9] | [0, 2, 8] |
---|---|---|---|---|---|
IOB1:NDRIVE | [0, 2, 39] | [0, 2, 38] | [0, 2, 37] | [0, 2, 36] | [0, 2, 35] |
IOB2:NDRIVE | [0, 2, 66] | [0, 2, 65] | [0, 2, 64] | [0, 2, 63] | [0, 2, 62] |
IOB3:NDRIVE | [1, 2, 12] | [1, 2, 11] | [1, 2, 10] | [1, 2, 9] | [1, 2, 8] |
IOB4:NDRIVE | [1, 2, 39] | [1, 2, 38] | [1, 2, 37] | [1, 2, 36] | [1, 2, 35] |
IOB5:NDRIVE | [1, 2, 66] | [1, 2, 65] | [1, 2, 64] | [1, 2, 63] | [1, 2, 62] |
Mixed inversion | [4] | [3] | ~[2] | ~[1] | [0] |
IOB0:IBUF_MODE | [0, 3, 15] | [0, 2, 15] | [0, 2, 16] |
---|---|---|---|
IOB1:IBUF_MODE | [0, 3, 42] | [0, 2, 42] | [0, 2, 43] |
IOB2:IBUF_MODE | [0, 3, 69] | [0, 2, 69] | [0, 2, 70] |
IOB3:IBUF_MODE | [1, 3, 15] | [1, 2, 15] | [1, 2, 16] |
IOB4:IBUF_MODE | [1, 3, 42] | [1, 2, 42] | [1, 2, 43] |
IOB5:IBUF_MODE | [1, 3, 69] | [1, 2, 69] | [1, 2, 70] |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:DISABLE_GTS | [0, 2, 18] |
---|---|
IOB1:DISABLE_GTS | [0, 2, 45] |
IOB2:DISABLE_GTS | [0, 2, 72] |
IOB3:DISABLE_GTS | [1, 2, 18] |
IOB4:DISABLE_GTS | [1, 2, 45] |
IOB4:VR | [1, 3, 48] |
IOB5:DISABLE_GTS | [1, 2, 72] |
IOB5:VR | [1, 3, 75] |
IOB5:VREF | [1, 3, 71] |
Non-inverted | [0] |
IOB0:DCI_MODE | [0, 2, 13] | [0, 2, 21] | [0, 3, 20] | [0, 2, 20] |
---|---|---|---|---|
IOB1:DCI_MODE | [0, 2, 40] | [0, 2, 48] | [0, 3, 47] | [0, 2, 47] |
IOB2:DCI_MODE | [0, 2, 67] | [0, 2, 75] | [0, 3, 74] | [0, 2, 74] |
IOB3:DCI_MODE | [1, 2, 13] | [1, 2, 21] | [1, 3, 20] | [1, 2, 20] |
IOB4:DCI_MODE | [1, 2, 40] | [1, 2, 48] | [1, 3, 47] | [1, 2, 47] |
IOB5:DCI_MODE | [1, 2, 67] | [1, 2, 75] | [1, 3, 74] | [1, 2, 74] |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:OUTPUT_DIFF | [0, 2, 33] | [0, 2, 19] | [0, 2, 6] | [0, 2, 46] |
---|---|---|---|---|
IOB2:OUTPUT_DIFF | [1, 2, 6] | [0, 2, 73] | [0, 2, 60] | [1, 2, 19] |
IOB4:OUTPUT_DIFF | [1, 2, 60] | [1, 2, 46] | [1, 2, 33] | [1, 2, 73] |
Non-inverted | [3] | [2] | [1] | [0] |
IOB0:SLEW | [0, 3, 4] | [0, 3, 8] | [0, 2, 4] | [0, 2, 5] | [0, 3, 5] |
---|---|---|---|---|---|
IOB1:SLEW | [0, 3, 31] | [0, 3, 35] | [0, 2, 31] | [0, 2, 32] | [0, 3, 32] |
IOB2:SLEW | [0, 3, 58] | [0, 3, 62] | [0, 2, 58] | [0, 2, 59] | [0, 3, 59] |
IOB3:SLEW | [1, 3, 4] | [1, 3, 8] | [1, 2, 4] | [1, 2, 5] | [1, 3, 5] |
IOB4:SLEW | [1, 3, 31] | [1, 3, 35] | [1, 2, 31] | [1, 2, 32] | [1, 3, 32] |
IOB5:SLEW | [1, 3, 58] | [1, 3, 62] | [1, 2, 58] | [1, 2, 59] | [1, 3, 59] |
Non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB0:DCIUPDATEMODE_ASREQUIRED | [0, 3, 6] |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | [0, 3, 33] |
IOB2:DCIUPDATEMODE_ASREQUIRED | [0, 3, 60] |
IOB3:DCIUPDATEMODE_ASREQUIRED | [1, 3, 6] |
IOB4:DCIUPDATEMODE_ASREQUIRED | [1, 3, 33] |
IOB5:DCIUPDATEMODE_ASREQUIRED | [1, 3, 60] |
Inverted | ~[0] |
IOB0:PDRIVE | [0, 3, 12] | [0, 3, 11] | [0, 3, 10] | [0, 3, 9] |
---|---|---|---|---|
IOB1:PDRIVE | [0, 3, 39] | [0, 3, 38] | [0, 3, 37] | [0, 3, 36] |
IOB2:PDRIVE | [0, 3, 66] | [0, 3, 65] | [0, 3, 64] | [0, 3, 63] |
IOB3:PDRIVE | [1, 3, 12] | [1, 3, 11] | [1, 3, 10] | [1, 3, 9] |
IOB4:PDRIVE | [1, 3, 39] | [1, 3, 38] | [1, 3, 37] | [1, 3, 36] |
IOB5:PDRIVE | [1, 3, 66] | [1, 3, 65] | [1, 3, 64] | [1, 3, 63] |
Mixed inversion | [3] | [2] | ~[1] | ~[0] |
IOB0:PULL | [0, 3, 14] | [0, 2, 14] | [0, 3, 13] |
---|---|---|---|
IOB1:PULL | [0, 3, 41] | [0, 2, 41] | [0, 3, 40] |
IOB2:PULL | [0, 3, 68] | [0, 2, 68] | [0, 3, 67] |
IOB3:PULL | [1, 3, 14] | [1, 2, 14] | [1, 3, 13] |
IOB4:PULL | [1, 3, 41] | [1, 2, 41] | [1, 3, 40] |
IOB5:PULL | [1, 3, 68] | [1, 2, 68] | [1, 3, 67] |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |