Project Combine
Contents:
Xilinx XC9500, XC9500XL, XC9500XV CPLDs
Xilinx XPLA3 CPLDs
Xilinx Coolrunner II CPLDs
Xilinx FPGAs
XC5200
Virtex
Virtex 2
Introduction
Device geometry
General interconnect
Configurable Logic Block
Block RAM — Virtex 2, Spartan 3
Clock interconnect
Input / Output
Digital Clock Managers
Hard PowerPC 405 cores
Multi-gigabit transceivers — Virtex 2 Pro
Multi-gigabit transceivers — Virtex 2 Pro X
Hard PCI logic
Corners
Configuration registers
Spartan 3
FPGAcore
Spartan 6
Virtex 4
Virtex 5
Virtex 6
Virtex 7
Project Combine
Xilinx FPGAs
Virtex 2
Hard PCI logic
View page source
Hard PCI logic
Todo
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